Intel ARCHITECTURE IA-32 User Manual download pdf (Page 72)

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2-24 Vol. 3A

SYSTEM ARCHITECTURE OVERVIEW

2.5.1 CPUID Qualification of Control Register Flags

The VME, PVI, TSD, DE, PSE, PAE, MCE, PGE, PCE, OSFXSR, and OSXMMEXCPT flags

in control register CR4 are model specific. All of these flags (except the PCE flag) can be qual-

ified with the CPUID instruction to determine if they are implemented on the processor before

they are used.

The CR8 register is available on processors that support Intel EM64T. Support for Intel EM64T

can determined using CPUID.

2.6 SYSTEM INSTRUCTION SUMMARY

System instructions handle system-level functions such as loading system registers, managing

the cache, managing interrupts, or setting up the debug registers. Many of these instructions can

be executed only by operating-system or executive procedures (that is, procedures running at

privilege level 0). Others can be executed at any privilege level and are thus available to appli-

cation programs.

Table 2-2 lists the system instructions and indicates whether they are available and useful for

application programs. These instructions are described in Chapter 3 and Chapter 4 of the IA-32

Intel® Architecture Software Developer’s Manual, Volumes 2A & 2B.

Table 2-2. Summary of System Instructions

Instruction Description

Useful to

Application?

Protected from

Application?

LLDT Load LDT Register No Yes

SLDT Store LDT Register No No

LGDT Load GDT Register No Yes

SGDT Store GDT Register No No

LTR Load Task Register No Yes

STR Store Task Register No No

LIDT Load IDT Register No Yes

SIDT Store IDT Register No No

MOV CRn Load and store control registers No Yes

SMSW Store MSW Yes No

LMSW Load MSW No Yes

CLTS Clear TS flag in CR0 No Yes

ARPL Adjust RPL Yes

1, 5

LAR Load Access Rights Yes No

LSL Load Segment Limit Yes No

VERR Verify for Reading Yes No

VERW Verify for Writing Yes No

1 2 ... 67 68 69 70 71 72 73 74 75 76 77 ... 635 636

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