Intel ARCHITECTURE IA-32 User Manual download pdf (Page 532)

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14-6 Vol. 3A

MACHINE-CHECK ARCHITECTURE

14.3.2.2 IA32_MCi_STATUS MSRs

Each IA32_MCi_STATUS MSR (called MCi_STATUS in P6 family processors) contains infor-

mation related to a machine-check error if its VAL (valid) flag is set (see Figure 14-6). Software

is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing

1s to them causes a general-protection exception.

Where:

• MCA (machine-check architecture) error code field, bits 0 through 15 — Specifies the

machine-check architecture-defined error code for the machine-check error condition

detected. The machine-check architecture-defined error codes are guaranteed to be the

same for all IA-32 processors that implement the machine-check architecture. See Section

14.6., “Interpreting the MCA Error Codes,” and Appendix E, “Interpreting Machine-

Check Error Codes,” for information on machine-check error codes.

• Model-specific error code field, bits 16 through 31 — Specifies the model-specific error

code that uniquely identifies the machine-check error condition detected. The model-

specific error codes may differ among IA-32 processors for the same machine-check error

condition. See Appendix E, “Interpreting Machine-Check Error Codes,” for information

on model-specific error codes.

• Other information field, bits 32 through 56 — The functions of these bits are implemen-

tation specific and are not part of the machine-check architecture. Software that is intended

to be portable among IA-32 processors should not rely on these values.

• PCC (processor context corrupt) flag, bit 57 — Indicates (when set) that the state of the

processor might have been corrupted by the error condition detected and that reliable

restarting of the processor may not be possible. When clear, this flag indicates that the

error did not affect the processor’s state.

• ADDRV (IA32_MCi_ADDR register valid) flag, bit 58 — Indicates (when set) that the

IA32_MCi_ADDR register contains the address where the error occurred (see Section

14.3.2.3, “IA32_MCi_ADDR MSRs”). When clear, this flag indicates that the

IA32_MCi_ADDR register is either not implemented or does not contain the address

Figure 14-6. IA32_MCi_STATUS Register

PCC—Processor context corrupt

63 062 6160 5958 5756 32 31 16 15

Other Information

Model-Specific

MCA Error Code

Error Code

ADDRV—MCi_ADDR register valid

MISCV—MCi_MISC register valid

EN—Error enabled

UC—Uncorrected error

OVER—Error overflow

VAL—MCi_STATUS register valid

1 2 ... 527 528 529 530 531 532 533 534 535 536 537 ... 635 636

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