Intel ARCHITECTURE IA-32 User Manual download pdf (Page 623)

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Vol. 3A 17-31

IA-32 ARCHITECTURE COMPATIBILITY

general-protection exceptions (#GP). Figure 17-1 demonstrates the different areas accessed by

the Intel486 and the P6 family and Pentium processors.

17.28. CACHE MANAGEMENT

The P6 family processors include two levels of internal caches: L1 (level 1) and L2 (level 2).

The L1 cache is divided into an instruction cache and a data cache; the L2 cache is a general-

purpose cache. See Section 10.1, “Internal Caches, TLBs, and Buffers,” for a description of

these caches. (Note that although the Pentium II processor L2 cache is physically located on a

separate chip in the cassette, it is considered an internal cache.)

The Pentium processor includes separate level 1 instruction and data caches. The data cache

supports a writeback (or alternatively write-through, on a line by line basis) policy for memory

updates.

The Intel486 processor includes a single level 1 cache for both instructions and data.

The meaning of the CD and NW flags in control register CR0 have been redefined for the P6

family and Pentium processors. For these processors, the recommended value (00B) enables

writeback for the data cache of the Pentium processor and for the L1 data cache and L2 cache

of the P6 family processors. In the Intel486 processor, setting these flags to (00B) enables write-

through for the cache.

Figure 17-1. I/O Map Base Address Differences

Intel486 Processor

FFFFH

I/O Map

Base Addres

FFFFH

FFFFH + 10H = FH

for I/O Validation

FFFFH

I/O access at port 10H checks

FFFFH + 10H = Outside Segment

for I/O Validation

bitmap at I/O address FFFFH + 10H,

which exceeds segment limit.

Wrap around does not occur,

general-protection exception (#GP)

I/O access at port 10H checks

bitmap at I/O map base address

FFFFH + 10H = offset 10H.

Offset FH from beginning of

TSS segment results because

P6 family and Pentium Processors

I/O Map

Base Addres

occurs. wraparound occurs.

1 2 ... 618 619 620 621 622 623 624 625 626 627 628 ... 635 636

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