Intel ARCHITECTURE IA-32 User Manual download pdf (Page 302)

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MULTIPLE-PROCESSOR MANAGEMENT

7.9.2 Memory Type Range Registers (MTRR)

MTRR is shared between two logical processors sharing a processor core if the physical

processor supports Hyper-Threading Technology. MTRR is not shared between logical proces-

sors located in different cores or different physical packages.

IA-32 architecture requires that all MP systems based on IA-32 processors (this includes logical

processors) use an identical MTRR memory map. This gives software a consistent view of

memory, independent of the processor on which it is running.

See Section 10.11, “Memory Type Range Registers (MTRRs).”

7.9.3 Performance Monitoring Counters

Performance counters and their companion control MSRs are shared between two logical

processors sharing a processor core if the physical package supports Hyper-Threading Tech-

nology. They are not shared between logical processors in different cores or different physical

packages. As a result, software must manage the use of these resources, based on the topology

of performance monitoring resources. Performance counter interrupts, events, and precise event

monitoring support can be set up and allocated on a per thread (per logical processor) basis.

See Section 18.14, “Performance Monitoring and Hyper-Threading Technology.”

7.9.4 IA32_MISC_ENABLE MSR

The IA32_MISC_ENABLE MSR (MSR address 1A0H) is shared between two logical proces-

sors sharing a processor core if the physical package supports Hyper-Threading Technology.

The MSR is not shared between logical processors in different cores or different physical pack-

ages. This means that the architectural features that this register controls are set the same for the

logical processors in the same core.

7.9.5 MICROCODE UPDATE Resources

Microcode update facilities are shared between two logical processors sharing a processor core

if the physical package supports Hyper-Threading Technology. They are not shared between

logical processors in different cores or different physical packages. Either logical processor that

has access to the microcode update facility can initiate an update.

Each logical processor has its own BIOS signature MSR (IA32_BIOS_SIGN_ID at MSR

address 8BH). When a logical processor performs an update for the physical processor, the

IA32_BIOS_SIGN_ID MSRs for resident logical processors are updated with identical infor-

mation. If logical processors initiate an update simultaneously, the processor core provides the

synchronization needed to ensure that only one update is performed at a time.

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