Intel ARCHITECTURE IA-32 User Manual download pdf (Page 108)

3-28 Vol. 3A

PROTECTED-MODE MEMORY MANAGEMENT

3. Invalidate the current page-table entry in the TLB (see Section 3.12,

“Translation Lookaside Buffers (TLBs)”, for a discussion of TLBs and

how to invalidate them).

4. Return from the page-fault handler to restart the interrupted program (or

task).

Read/write (R/W) flag, bit 1

Specifies the read-write privileges for a page or group of pages (in the case of

a page-directory entry that points to a page table). When this flag is clear, the

page is read only; when the flag is set, the page can be read and written into.

This flag interacts with the U/S flag and the WP flag in register CR0. See

Section 4.11, “Page-Level Protection”, and Table 4-3 for a detailed discussion

of the use of these flags.

User/supervisor (U/S) flag, bit 2

Specifies the user-supervisor privileges for a page or group of pages (in the

case of a page-directory entry that points to a page table). When this flag is

clear, the page is assigned the supervisor privilege level; when the flag is set,

the page is assigned the user privilege level. This flag interacts with the R/W

flag and the WP flag in register CR0. See Section 4.11, “Page-Level Protec-

tion”, and Table 4-3 for a detail discussion of the use of these flags.

Page-level write-through (PWT) flag, bit 3

Controls the write-through or write-back caching policy of individual pages or

page tables. When the PWT flag is set, write-through caching is enabled for the

associated page or page table; when the flag is clear, write-back caching is

enabled for the associated page or page table. The processor ignores this flag if

the CD (cache disable) flag in CR0 is set. See Section 10.5, “Cache Control”,

for more information about the use of this flag. See Section 2.5, “Control

Registers”, for a description of a companion PWT flag in control register CR3.

Page-level cache disable (PCD) flag, bit 4

Controls the caching of individual pages or page tables. When the PCD flag is

set, caching of the associated page or page table is prevented; when the flag is

clear, the page or page table can be cached. This flag permits caching to be

disabled for pages that contain memory-mapped I/O ports or that do not

provide a performance benefit when cached. The processor ignores this flag

(assumes it is set) if the CD (cache disable) flag in CR0 is set. See Chapter 10,

“Memory Cache Control”, for more information about the use of this flag. See

Section 2.5, “Control Registers”, for a description of a companion PCD flag in

control register CR3.

Accessed (A) flag, bit 5

Indicates whether a page or page table has been accessed (read from or written

to) when set. Memory management software typically clears this flag when a

page or page table is initially loaded into physical memory. The processor then

sets this flag the first time a page or page table is accessed.

1 2 ... 103 104 105 106 107 108 109 110 111 112 113 ... 635 636

Comments to this Manuals

No comments

Intel ARCHITECTURE IA-32 User Manual Page 108

Comments to this Manuals

Related products and manuals for Processors Intel ARCHITECTURE IA-32