Intel ARCHITECTURE IA-32 User Manual download pdf (Page 255)

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Vol. 3A 6-13

TASK MANAGEMENT

JMP, CALL, and IRET instructions, as well as interrupts and exceptions, are all mechanisms for

redirecting a program. The referencing of a TSS descriptor or a task gate (when calling or

jumping to a task) or the state of the NT flag (when executing an IRET instruction) determines

whether a task switch occurs.

The processor performs the following operations when switching to a new task:

1. Obtains the TSS segment selector for the new task as the operand of the JMP or CALL

instruction, from a task gate, or from the previous task link field (for a task switch initiated

with an IRET instruction).

2. Checks that the current (old) task is allowed to switch to the new task. Data-access

privilege rules apply to JMP and CALL instructions. The CPL of the current (old) task and

the RPL of the segment selector for the new task must be less than or equal to the DPL of

the TSS descriptor or task gate being referenced. Exceptions, interrupts (except for

interrupts generated by the INT n instruction), and the IRET instruction are permitted to

switch tasks regardless of the DPL of the destination task-gate or TSS descriptor. For

interrupts generated by the INT n instruction, the DPL is checked.

3. Checks that the TSS descriptor of the new task is marked present and has a valid limit

(greater than or equal to 67H).

4. Checks that the new task is available (call, jump, exception, or interrupt) or busy (IRET

return).

5. Checks that the current (old) TSS, new TSS, and all segment descriptors used in the task

switch are paged into system memory.

6. If the task switch was initiated with a JMP or IRET instruction, the processor clears the

busy (B) flag in the current (old) task’s TSS descriptor; if initiated with a CALL

instruction, an exception, or an interrupt: the busy (B) flag is left set. (See Table 6-2.)

7. If the task switch was initiated with an IRET instruction, the processor clears the NT flag

in a temporarily saved image of the EFLAGS register; if initiated with a CALL or JMP

instruction, an exception, or an interrupt, the NT flag is left unchanged in the saved

EFLAGS image.

8. Saves the state of the current (old) task in the current task’s TSS. The processor finds the

base address of the current TSS in the task register and then copies the states of the

following registers into the current TSS: all the general-purpose registers, segment

selectors from the segment registers, the temporarily saved image of the EFLAGS register,

and the instruction pointer register (EIP).

9. If the task switch was initiated with a CALL instruction, an exception, or an interrupt, the

processor will set the NT flag in the EFLAGS loaded from the new task. If initiated with an

IRET instruction or JMP instruction, the NT flag will reflect the state of NT in the

EFLAGS loaded from the new task (see Table 6-2).

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Intel ARCHITECTURE IA-32 User Manual Page 255

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