Intel ARCHITECTURE IA-32 User Manual download pdf (Page 65)

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Vol. 3A 2-17

SYSTEM ARCHITECTURE OVERVIEW

The control registers are summarized below, and each architecturally defined control field in

these control registers are described individually. In Figure 2-6, the width of the register in

64-bit mode is indicated in parenthesis (except for CR0).

• CR0 — Contains system control flags that control operating mode and states of the

processor.

• CR1 — Reserved.

• CR2 — Contains the page-fault linear address (the linear address that caused a page fault).

• CR3 — Contains the physical address of the base of the page directory and two flags (PCD

and PWT). This register is also known as the page-directory base register (PDBR). Only

the most-significant bits (less the lower 12 bits) of the base address are specified; the lower

12 bits of the address are assumed to be 0. The page directory must thus be aligned to a

page (4-KByte) boundary. The PCD and PWT flags control caching of the page directory

in the processor’s internal data caches (they do not control TLB caching of page-directory

information).

When using the physical address extension, the CR3 register contains the base address of

the page-directory-pointer table In IA-32e mode, the CR3 register contains the base

address of the PML4 table.

See also: Section 3.8, “36-Bit Physical Addressing Using the PAE Paging Mechanism.”

• CR4 — Contains a group of flags that enable several architectural extensions, and indicate

operating system or executive support for specific processor capabilities. The control

registers can be read and loaded (or modified) using the move-to-or-from-control-registers

forms of the MOV instruction. In protected mode, the MOV instructions allow the control

registers to be read or loaded (at privilege level 0 only). This restriction means that

application programs or operating-system procedures (running at privilege levels 1, 2, or

3) are prevented from reading or loading the control registers.

• CR8 — Provides read and write access to the Task Priority Register (TPR). It specifies the

priority threshold value that operating systems use to control the priority class of external

interrupts allowed to interrupt the processor. This register is available only in 64-bit mode.

However, interrupt filtering continues to apply in compatibility mode.

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