Intel ARCHITECTURE IA-32 User Manual download pdf (Page 454)

10-14 Vol. 3A

MEMORY CACHE CONTROL

• NW flag, bit 29 of control register CR0 — Controls the write policy for system memory

locations (see Section 2.5, “Control Registers”). If the NW and CD flags are clear, write-

back is enabled for the whole of system memory, but may be restricted for individual pages

or regions of memory by other cache-control mechanisms. Table 10-5 shows how the other

combinations of CD and NW flags affects caching.

NOTES

For the Pentium 4 and Intel Xeon processors, the NW flag is a don’t care flag;

that is, when the CD flag is set, the processor uses the no-fill cache mode,

regardless of the setting of the NW flag.

For the Pentium processor, when the L1 cache is disabled (the CD and NW

flags in control register CR0 are set), external snoops are accepted in DP

(dual-processor) systems and inhibited in uniprocessor systems.

When snoops are inhibited, address parity is not checked and APCHK# is not

asserted for a corrupt address; however, when snoops are accepted, address

parity is checked and APCHK# is asserted for corrupt addresses.

• PCD flag in the page-directory and page-table entries — Controls caching for

individual page tables and pages, respectively (see Section 3.7.6, “Page-Directory and

Page-Table Entries”). This flag only has effect when paging is enabled and the CD flag in

control register CR0 is clear. The PCD flag enables caching of the page table or page when

clear and prevents caching when set.

• PWT flag in the page-directory and page-table entries — Controls the write policy for

individual page tables and pages, respectively (see Section 3.7.6, “Page-Directory and

Page-Table Entries”). This flag only has effect when paging is enabled and the NW flag in

control register CR0 is clear. The PWT flag enables write-back caching of the page table or

page when clear and write-through caching when set.

• PCD and PWT flags in control register CR3 — Control the global caching and write

policy for the page directory (see Section 2.5, “Control Registers”). The PCD flag enables

caching of the page directory when clear and prevents caching when set. The PWT flag

enables write-back caching of the page directory when clear and write-through caching

when set. These flags do not affect the caching and write policy for individual page tables.

These flags only have effect when paging is enabled and the CD flag in control register

CR0 is clear.

• G (global) flag in the page-directory and page-table entries (introduced to the IA-32

architecture in the P6 family processors) — Controls the flushing of TLB entries for

individual pages. See Section 3.12, “Translation Lookaside Buffers (TLBs),” for more

information about this flag.

• PGE (page global enable) flag in control register CR4 — Enables the establishment of

global pages with the G flag. See Section 3.12, “Translation Lookaside Buffers (TLBs),”

for more information about this flag.

1 2 ... 449 450 451 452 453 454 455 456 457 458 459 ... 635 636

No comments

Intel ARCHITECTURE IA-32 User Manual Page 454