Intel ARCHITECTURE IA-32 User Manual download pdf (Page 603)

Vol. 3A 17-11

IA-32 ARCHITECTURE COMPATIBILITY

17.17.5.1 NANS

The 32-bit x87 FPUs distinguish between signaling NaNs (SNaNs) and quiet NaNs (QNaNs).

These x87 FPUs only generate QNaNs and normally do not generate an exception upon encoun-

tering a QNaN. An invalid-operation exception (#I) is generated only upon encountering a

SNaN, except for the FCOM, FIST, and FBSTP instructions, which also generates an invalid-

operation exceptions for a QNaNs. This behavior matches IEEE Standard 754.

The 16-bit IA-32 math coprocessors only generate one kind of NaN (the equivalent of a QNaN),

but the raise an invalid-operation exception upon encountering any kind of NaN.

When porting software written to run on a 16-bit IA-32 math coprocessor to a 32-bit x87 FPU,

uninitialized memory locations that contain QNaNs should be changed to SNaNs to cause the

x87 FPU or math coprocessor to fault when uninitialized memory locations are referenced.

17.17.5.2 PSEUDO-ZERO, PSEUDO-NAN, PSEUDO-INFINITY, AND

UNNORMAL FORMATS

The 32-bit x87 FPUs neither generate nor support the pseudo-zero, pseudo-NaN, pseudo-

infinity, and unnormal formats. Whenever they encounter them in an arithmetic operation, they

raise an invalid-operation exception. The 16-bit IA-32 math coprocessors define and support

special handling for these formats. Support for these formats was dropped to conform with IEEE

Standard 754 for Binary Floating-Point Arithmetic.

This change should not impact software ported from 16-bit IA-32 math coprocessors to 32-bit

x87 FPUs. The 32-bit x87 FPUs do not generate these formats, and therefore will not encounter

them unless software explicitly loads them in the data registers. The only affect may be in how

software handles the tags in the tag word (see also: Section 17.17.4, “x87 FPU Tag Word”).

17.17.6 Floating-Point Exceptions

This section identifies the implementation differences in exception handling for floating-point

instructions in the various x87 FPUs and math coprocessors.

17.17.6.1 DENORMAL OPERAND EXCEPTION (#D)

When the denormal operand exception is masked, the 32-bit x87 FPUs automatically normalize

denormalized numbers when possible; whereas, the 16-bit IA-32 math coprocessors return a

denormal result. A program written to run on a 16-bit IA-32 math coprocessor that uses the

denormal exception solely to normalize denormalized operands is redundant when run on the

32-bit x87 FPUs. If such a program is run on 32-bit x87 FPUs, performance can be improved by

masking the denormal exception. Floating-point programs run faster when the FPU performs

normalization of denormalized operands.

The denormal operand exception is not raised for transcendental instructions and the FXTRACT

instruction on the 16-bit IA-32 math coprocessors. This exception is raised for these instructions

on the 32-bit x87 FPUs. The exception handlers ported to these latter processors need to be

changed only if the handlers gives special treatment to different opcodes.

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Intel ARCHITECTURE IA-32 User Manual Page 603