Intel ARCHITECTURE IA-32 User Manual download pdf (Page 290)

7-22 Vol. 3A

MULTIPLE-PROCESSOR MANAGEMENT

7.5.5 Identifying Logical Processors in an MP System

After the BIOS has completed the MP initialization protocol, each logical processor can be

uniquely identified by its local APIC ID. Software can access these APIC IDs in either of the

following ways:

• Read APIC ID for a local APIC — Code running on a logical processor can execute a

MOV instruction to read the processor’s local APIC ID register (see Section 8.4.6, “Local

APIC ID”). This is the ID to use for directing physical destination mode interrupts to the

processor.

• Read ACPI or MP table — As part of the MP initialization protocol, the BIOS creates an

ACPI table and an MP table. These tables are defined in the Multiprocessor Specification

Version 1.4 and provide software with a list of the processors in the system and their local

APIC IDs. The format of the ACPI table is derived from the ACPI specification, which is

an industry standard power management and platform configuration specification for MP

systems.

• Read Initial APIC ID — An APIC ID is assigned to a logical processor during power up

and is called the initial APIC ID. This is the APIC ID reported by CPUID.1:ECX[31:24]

and may be different from the current value read from the local APIC. Use the initial APIC

ID to determine the topological relationship between logical processors.

Bits in the initial APIC ID can be interpreted using several bit masks. Each bit mask can be

used to extract an identifier to represent a hierarchical level of the multi-threading resource

topology in an MP system (See Section 7.10.1, “Hierarchical Mapping of Shared

Resources”). The initial APIC ID may consist of up to four bit-fields. In a non-clustered

MP system, the field consists of up to three bit fields.

Figure 7-2 shows APIC ID bit fields in earlier single-core processors. For Intel Xeon processors,

the APIC ID assigned to a logical processor during power-up and initialization is 8 bits. Bits 2:1

form a 2-bit physical package identifier (which can also be thought of as a socket identifier). In

systems that configure physical processors in clusters, bits 4:3 form a 2-bit cluster ID. Bit 0 is

used in the Intel Xeon processor MP to identify the two logical processors within the package

(see Section 7.10.2, “Identifying Logical Processors in an MP System”). For Intel Xeon proces-

sors that do not support Intel Hyper-Threading Technology, bit 0 is always set to 0; for Intel

Xeon processors supporting Hyper-Threading Technology, bit 0 performs the same function as

it does for Intel Xeon processor MP.

See Section 7.10.1, “Hierarchical Mapping of Shared Resources” for a complete description of

the topological relationships between logical processors and bit field locations within an initial

APIC ID across IA-32 processor families.

Note the number of bit fields and the width of bit-fields are dependent on processor and platform

hardware capabilities. Determine these at runtime. When initial APIC IDs are assigned to logical

processors, the value of APIC ID assigned to a logical processor will respect the bit-field bound-

aries corresponding core, physical package, etc. Additional examples of the bit fields in the

initial APIC ID of multi-threading capable systems are shown in Section 7.10.

1 2 ... 285 286 287 288 289 290 291 292 293 294 295 ... 635 636

No comments

Intel ARCHITECTURE IA-32 User Manual Page 290