Intel ARCHITECTURE IA-32 User Manual download pdf (Page 611)

Vol. 3A 17-19

IA-32 ARCHITECTURE COMPATIBILITY

17.17.11Operands Split Across Segments and/or Pages

On the P6 family, Pentium, and Intel486 processor FPUs, when the first half of an operand to be

written is inside a page or segment and the second half is outside, a memory fault can cause the

first half to be stored but not the second half. In this situation, the Intel 387 math coprocessor

stores nothing.

17.17.12FPU Instruction Synchronization

On the 32-bit x87 FPUs, all floating-point instructions are automatically synchronized; that is,

the processor automatically waits until the previous floating-point instruction has completed

before completing the next floating-point instruction. No explicit WAIT/FWAIT instructions are

required to assure this synchronization. For the 8087 math coprocessors, explicit waits are

required before each floating-point instruction to ensure synchronization. Although 8087

programs having explicit WAIT instructions execute perfectly on the 32-bit IA-32 processors

without reassembly, these WAIT instructions are unnecessary.

17.18. SERIALIZING INSTRUCTIONS

Certain instructions have been defined to serialize instruction execution to ensure that modifi-

cations to flags, registers and memory are completed before the next instruction is executed (or

in P6 family processor terminology “committed to machine state”). Because the P6 family

processors use branch-prediction and out-of-order execution techniques to improve perfor-

mance, instruction execution is not generally serialized until the results of an executed instruc-

tion are committed to machine state (see Chapter 2, “IA-32 Intel® Architecture,” in the IA-32

Intel® Architecture Software Developer’s Manual, Volume 1).

As a result, at places in a program or task where it is critical to have execution completed for all

previous instructions before executing the next instruction (for example, at a branch, at the end

of a procedure, or in multiprocessor dependent code), it is useful to add a serializing instruction.

See Section 7.4, “Serializing Instructions,” for more information on serializing instructions.

17.19. FPU AND MATH COPROCESSOR INITIALIZATION

Table 9-1 shows the states of the FPUs in the P6 family, Pentium, Intel486 processors and of the

Intel 387 math coprocessor and Intel 287 coprocessor following a power-up, reset, or INIT, or

following the execution of an FINIT/FNINIT instruction. The following is some additional

compatibility information concerning the initialization of x87 FPUs and math coprocessors.

17.19.1 Intel

387 and Intel

287 Math Coprocessor Initialization

Following an Intel386 processor reset, the processor identifies its coprocessor type (Intel

287

or Intel

387 DX math coprocessor) by sampling its ERROR# input some time after the falling

edge of RESET# signal and before execution of the first floating-point instruction. The Intel 287

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Intel ARCHITECTURE IA-32 User Manual Page 611