Intel ARCHITECTURE IA-32 User Manual download pdf (Page 56)

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SYSTEM ARCHITECTURE OVERVIEW

The location of pages (sometimes called page frames) in physical memory is contained in two

types of system data structures: page directories and page tables. Both structures reside in phys-

ical memory (see Figure 2-1).

The base physical address of the page directory is contained in control register CR3. An entry

in a page directory contains the physical address of the base of a page table, access rights and

memory management information. An entry in a page table contains the physical address of a

page frame, access rights and memory management information.

To use this paging mechanism, a linear address is broken into three parts. The parts provide sepa-

rate offsets into the page directory, the page table, and the page frame. A system can have a

single page directory or several. For example, each task can have its own page directory.

2.1.5.1 Memory Management in IA-32e Mode

In IA-32e mode, physical memory pages are managed by a set of system data structures. In

compatibility mode and 64-bit mode, four levels of system data structures are used. These

include:

• The page map level 4 (PML4) — An entry in a PML4 table contains the physical address

of the base of a page directory pointer table, access rights, and memory management infor-

mation. The base physical address of the PML4 is stored in CR3.

• A set of page directory pointers — An entry in a page directory pointer table contains the

physical address of the base of a page directory table, access rights, and memory

management information.

• Sets of page directories — An entry in a page directory table contains the physical

address of the base of a page table, access rights, and memory management information.

• Sets of page tables — An entry in a page table contains the physical address of a page

frame, access rights, and memory management information.

2.1.6 System Registers

To assist in initializing the processor and controlling system operations, the system architecture

provides system flags in the EFLAGS register and several system registers:

• The system flags and IOPL field in the EFLAGS register control task and mode switching,

interrupt handling, instruction tracing, and access rights. See also: Section 2.3, “System

Flags and Fields in the EFLAGS Register.”

• The control registers (CR0, CR2, CR3, and CR4) contain a variety of flags and data fields

for controlling system-level operations. Other flags in these registers are used to indicate

support for specific processor capabilities within the operating system or executive. See

also: Section 2.5, “Control Registers.”

• The debug registers (not shown in Figure 2-1) allow the setting of breakpoints for use in

debugging programs and systems software. See also: Chapter 18, “Debugging and

Performance Monitoring.”

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