Intel ARCHITECTURE IA-32 User Manual download pdf (Page 393)

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Vol. 3A 9-19

PROCESSOR MANAGEMENT AND INITIALIZATION

4. Load segment registers SS, DS, ES, FS, and GS with a selector for a descriptor containing

the following values, which are appropriate for real-address mode:

— Limit = 64 KBytes (0FFFFH)

— Byte granular (G = 0)

— Expand up (E = 0)

— Writable (W = 1)

—Present (P = 1)

— Base = any value

The segment registers must be loaded with non-null segment selectors or the segment

registers will be unusable in real-address mode. Note that if the segment registers are not

reloaded, execution continues using the descriptor attributes loaded during protected

mode.

5. Execute an LIDT instruction to point to a real-address mode interrupt table that is within

the 1-MByte real-address mode address range.

6. Clear the PE flag in the CR0 register to switch to real-address mode.

7. Execute a far JMP instruction to jump to a real-address mode program. This operation

flushes the instruction queue and loads the appropriate base and access rights values in the

CS register.

8. Load the SS, DS, ES, FS, and GS registers as needed by the real-address mode code. If any

of the registers are not going to be used in real-address mode, write 0s to them.

9. Execute the STI instruction to enable maskable hardware interrupts and perform the

necessary hardware operation to enable NMI interrupts.

NOTE

All the code that is executed in steps 1 through 9 must be in a single page and

the linear addresses in that page must be identity mapped to physical

addresses.

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