Intel ARCHITECTURE IA-32 User Manual download pdf (Page 441)

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Vol. 3A 10-1

CHAPTER 10

MEMORY CACHE CONTROL

This chapter describes the IA-32 architecture’s memory cache and cache control mechanisms, the

TLBs, and the store buffer. It also describes the memory type range registers (MTRRs) found in

the P6 family processors and how they are used to control caching of physical memory locations.

10.1 INTERNAL CACHES, TLBS, AND BUFFERS

The IA-32 architecture supports caches, translation look aside buffers (TLBs), and a store buffer

for temporary on-chip (and external) storage of instructions and data. (Figure 10-1 shows the

arrangement of caches, TLBs, and the store buffer for the Pentium 4 and Intel Xeon processors.)

Table 10-1 shows the characteristics of these caches and buffers for the Pentium 4, Intel Xeon,

P6 family, and Pentium processors. The sizes and characteristics of these units are machine

specific and may change in future versions of the processor. The CPUID instruction returns

the sizes and characteristics of the caches and buffers for the processor on which the instruction

is executed (see “CPUID—CPU Identification” in Chapter 3, “Instruction Set Reference, A-M,”

of the IA-32 Intel® Architecture Software Developer’s Manual, Volume 2A).

Figure 10-1. Cache Structure of the Pentium 4 and Intel Xeon Processors

Trace Cache

Instruction Decoder

Bus Interface Unit

System Bus

Data Cache

Unit (L1)

(External)

Physical

Memory

Store Buffer

Data TLBs

L2 Cache

Instruction

TLBs

L3 Cache

†

† Intel Xeon processors only

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