Intel ARCHITECTURE IA-32 User Manual download pdf (Page 605)

Vol. 3A 17-13

IA-32 ARCHITECTURE COMPATIBILITY

16-bit IA-32 math coprocessors, it takes precedence over all other exceptions. This difference

causes no impact on existing software, but some unneeded normalization of denormalized oper-

ands is prevented on the Intel486 processor and Intel 387 math coprocessor.

17.17.6.5 CS AND EIP FOR FPU EXCEPTIONS

On the Intel 32-bit x87 FPUs, the values from the CS and EIP registers saved for floating-point

exceptions point to any prefixes that come before the floating-point instruction. On the 8087

math coprocessor, the saved CS and IP registers points to the floating-point instruction.

17.17.6.6 FPU ERROR SIGNALS

The floating-point error signals to the P6 family, Pentium, and Intel486 processors do not pass

through an interrupt controller; an INT# signal from an Intel 387, Intel 287 or 8087 math copro-

cessors does. If an 8086 processor uses another exception for the 8087 interrupt, both exception

vectors should call the floating-point-error exception handler. Some instructions in a floating-

point-error exception handler may need to be deleted if they use the interrupt controller. The P6

family, Pentium, and Intel486 processors have signals that, with the addition of external logic,

support reporting for emulation of the interrupt mechanism used in many personal computers.

On the P6 family, Pentium, and Intel486 processors, an undefined floating-point opcode will

cause an invalid-opcode exception (#UD, interrupt vector 6). Undefined floating-point opcodes,

like legal floating-point opcodes, cause a device not available exception (#NM, interrupt vector

7) when either the TS or EM flag in control register CR0 is set. The P6 family, Pentium, and

Intel486 processors do not check for floating-point error conditions on encountering an unde-

fined floating-point opcode.

17.17.6.7 ASSERTION OF THE FERR# PIN

When using the MS-DOS compatibility mode for handing floating-point exceptions, the FERR#

pin must be connected to an input to an external interrupt controller. An external interrupt is then

generated when the FERR# output drives the input to the interrupt controller and the interrupt

controller in turn drives the INTR pin on the processor.

For the P6 family and Intel386 processors, an unmasked floating-point exception always causes

the FERR# pin to be asserted upon completion of the instruction that caused the exception. For

the Pentium and Intel486 processors, an unmasked floating-point exception may cause the

FERR# pin to be asserted either at the end of the instruction causing the exception or immedi-

ately before execution of the next floating-point instruction. (Note that the next floating-point

instruction would not be executed until the pending unmasked exception has been handled.) See

Appendix D, “Guidelines for Writing x87 FPU Extension Handlers,” in the IA-32 Intel® Archi-

tecture Software Developer’s Manual, Volume 1, for a complete description of the required

mechanism for handling floating-point exceptions using the MS-DOS compatibility mode.

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Intel ARCHITECTURE IA-32 User Manual Page 605