Intel ARCHITECTURE IA-32 User Manual download pdf (Page 194)

5-18 Vol. 3A

INTERRUPT AND EXCEPTION HANDLING

An attempt to violate this rule results in a general-protection exception (#GP). The protection

mechanism for exception- and interrupt-handler procedures is different in the following ways:

• Because interrupt and exception vectors have no RPL, the RPL is not checked on implicit

calls to exception and interrupt handlers.

• The processor checks the DPL of the interrupt or trap gate only if an exception or interrupt

is generated with an INT n, INT 3, or INTO instruction. Here, the CPL must be less than or

equal to the DPL of the gate. This restriction prevents application programs or procedures

running at privilege level 3 from using a software interrupt to access critical exception

handlers, such as the page-fault handler, providing that those handlers are placed in more

privileged code segments (numerically lower privilege level). For hardware-generated

interrupts and processor-detected exceptions, the processor ignores the DPL of interrupt

and trap gates.

Because exceptions and interrupts generally do not occur at predictable times, these privilege

rules effectively impose restrictions on the privilege levels at which exception and interrupt-

handling procedures can run. Either of the following techniques can be used to avoid privilege-

level violations.

• The exception or interrupt handler can be placed in a conforming code segment. This

technique can be used for handlers that only need to access data available on the stack (for

example, divide error exceptions). If the handler needs data from a data segment, the data

segment needs to be accessible from privilege level 3, which would make it unprotected.

• The handler can be placed in a nonconforming code segment with privilege level 0. This

handler would always run, regardless of the CPL that the interrupted program or task is

running at.

5.12.1.2 Flag Usage By Exception- or Interrupt-Handler Procedure

When accessing an exception or interrupt handler through either an interrupt gate or a trap gate,

the processor clears the TF flag in the EFLAGS register after it saves the contents of the

EFLAGS register on the stack. (On calls to exception and interrupt handlers, the processor also

clears the VM, RF, and NT flags in the EFLAGS register, after they are saved on the stack.)

Clearing the TF flag prevents instruction tracing from affecting interrupt response. A subsequent

IRET instruction restores the TF (and VM, RF, and NT) flags to the values in the saved contents

of the EFLAGS register on the stack.

The only difference between an interrupt gate and a trap gate is the way the processor handles

the IF flag in the EFLAGS register. When accessing an exception- or interrupt-handling proce-

dure through an interrupt gate, the processor clears the IF flag to prevent other interrupts from

interfering with the current interrupt handler. A subsequent IRET instruction restores the IF flag

to its value in the saved contents of the EFLAGS register on the stack. Accessing a handler

procedure through a trap gate does not affect the IF flag.

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Intel ARCHITECTURE IA-32 User Manual Page 194