Intel ARCHITECTURE IA-32 User Manual download pdf (Page 31)

Vol. 3A xxxi

CONTENTS

PAGE

Table 6-1. Exception Conditions Checked During a Task Switch . . . . . . . . . . . . . . . . . 6-15

Table 6-2. Effect of a Task Switch on Busy Flag, NT Flag,

Previous Task Link Field, and TS Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17

Table 7-1. Initial APIC IDs for the Logical Processors in a System that has

Four MP-Type Intel Xeon Processors Supporting Hyper-Threading

Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37

Table 7-2. Initial APIC IDs for the Logical Processors in a System that has

Two Physical Processors Supporting Dual-Core and Hyper-Threading

Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37

Table 8-1. Local APIC Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

Table 8-2. ESR Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19

Table 8-3. Valid Combinations for the Pentium 4 and Intel Xeon Processors’

Local xAPIC Interrupt Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26

Table 8-4. Valid Combinations for the P6 Family Processors’

Local APIC Interrupt Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27

Table 9-1. IA-32 Processor States Following Power-up, Reset, or INIT . . . . . . . . . . . . . 9-3

Table 9-2. Recommended Settings of EM and MP Flags on IA-32 Processors. . . . . . . . 9-7

Table 9-3. Software Emulation Settings of EM, MP, and NE Flags . . . . . . . . . . . . . . . . . 9-8

Table 9-4. Main Initialization Steps in STARTUP.ASM Source Listing . . . . . . . . . . . . . 9-21

Table 9-5. Relationship Between BLD Item and ASM Source File . . . . . . . . . . . . . . . . 9-35

Table 9-6. Microcode Update Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37

Table 9-7. Microcode Update Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39

Table 9-8. Extended Processor Signature Table Header Structure. . . . . . . . . . . . . . . . 9-40

Table 9-9. Processor Signature Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40

Table 9-10. Processor Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-42

Table 9-11. Microcode Update Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-48

Table 9-12. Microcode Update Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-54

Table 9-13. Parameters for the Presence Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-55

Table 9-14. Parameters for the Write Update Data Function. . . . . . . . . . . . . . . . . . . . . . 9-56

Table 9-15. Parameters for the Control Update Sub-function . . . . . . . . . . . . . . . . . . . . . 9-61

Table 9-16. Mnemonic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-61

Table 9-17. Parameters for the Read Microcode Update Data Function. . . . . . . . . . . . . 9-62

Table 9-18. Return Code Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-63

Table 10-1. Characteristics of the Caches, TLBs, Store Buffer, and

Write Combining Buffer in IA-32 Processors. . . . . . . . . . . . . . . . . . . . . . . . . 10-2

Table 10-2. Memory Types and Their Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

Table 10-3. Methods of Caching Available in Pentium 4, Intel Xeon, P6 Family,

and Pentium Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

Table 10-4. MESI Cache Line States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10

Table 10-5. Cache Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13

Table 10-6. Effective Page-Level Memory Type for Pentium Pro and

Pentium II Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16

Table 10-7. Effective Page-Level Memory Types for Pentium III, Pentium 4,

and Intel Xeon Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17

Table 10-8. Memory Types That Can Be Encoded in MTRRs. . . . . . . . . . . . . . . . . . . . 10-25

Table 10-9. Address Mapping for Fixed-Range MTRRs . . . . . . . . . . . . . . . . . . . . . . . . 10-29

Table 10-10. Memory Types That Can Be Encoded With PAT . . . . . . . . . . . . . . . . . . . . 10-42

Table 10-11. Selection of PAT Entries with PAT, PCD, and PWT Flags . . . . . . . . . . . . . 10-43

Table 10-12. Memory Type Setting of PAT Entries Following a Power-up or Reset . . . . 10-43

Table 11-1. Action Taken By MMX Instructions for Different Combinations

of EM, MP and TS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

Table 11-2. Effects of MMX Instructions on x87 FPU State. . . . . . . . . . . . . . . . . . . . . . . 11-3

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 635 636

Comments to this Manuals

No comments

Intel ARCHITECTURE IA-32 User Manual Page 31

Comments to this Manuals

Related products and manuals for Processors Intel ARCHITECTURE IA-32