Intel ARCHITECTURE IA-32 User Manual download pdf (Page 455)

Vol. 3A 10-15

MEMORY CACHE CONTROL

• Memory type range registers (MTRRs) (introduced in P6 family processors) —

Control the type of caching used in specific regions of physical memory. Any of the

caching types described in Section 10.3, “Methods of Caching Available,” can be selected.

See Section 10.11, “Memory Type Range Registers (MTRRs),” for a detailed description

of the MTRRs.

• Page Attribute Table (PAT) MSR (introduced in the Pentium III processor) — Extends

the memory typing capabilities of the processor to permit memory types to be assigned on

a page-by-page basis (see Section 10.12, “Page Attribute Table (PAT)”).

• Third-Level Cache Disable flag, bit 6 of the IA32_MISC_ENABLE MSR (introduced

in the Intel Xeon processors) — Allows the L3 cache to be disabled and enabled,

independently of the L1 and L2 caches.

• KEN# and WB/WT# pins (Pentium processor) — Allow external hardware to control

the caching method used for specific areas of memory. They perform similar (but not

identical) functions to the MTRRs in the P6 family processors.

• PCD and PWT pins (Pentium processor) — These pins (which are associated with the

PCD and PWT flags in control register CR3 and in the page-directory and page-table

entries) permit caching in an external L2 cache to be controlled on a page-by-page basis,

consistent with the control exercised on the L1 cache of these processors. The Pentium 4,

Intel Xeon, and P6 family processors do not provide these pins because the L2 cache in

internal to the chip package.

10.5.2 Precedence of Cache Controls

The cache control flags and MTRRs operate hierarchically for restricting caching. That is, if the

CD flag is set, caching is prevented globally (see Table 10-5). If the CD flag is clear, the page-

level cache control flags and/or the MTRRs can be used to restrict caching. If there is an overlap

of page-level and MTRR caching controls, the mechanism that prevents caching has prece-

dence. For example, if an MTRR makes a region of system memory uncachable, a page-level

caching control cannot be used to enable caching for a page in that region. The converse is also

true; that is, if a page-level caching control designates a page as uncachable, an MTRR cannot

be used to make the page cacheable.

In cases where there is a overlap in the assignment of the write-back and write-through caching

policies to a page and a region of memory, the write-through policy takes precedence. The write-

combining policy (which can only be assigned through an MTRR or the PAT) takes precedence

over either write-through or write-back.

The selection of memory types at the page level varies depending on whether PAT is being used

to select memory types for pages, as described in the following sections.

Third-level cache disable flag (bit 6 of the IA32_MISC_ENABLE MSR) takes precedence over

the CD flag, MTRRs, and PAT for the L3 cache. That is, when the third-level cache disable flag

is set (cache disabled), the other cache controls have no affect on the L3 cache; when the flag is

clear (enabled), the cache controls have the same affect on the L3 cache as they have on the L1

and L2 caches.

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Intel ARCHITECTURE IA-32 User Manual Page 455