Intel ARCHITECTURE IA-32 User Manual download pdf (Page 40)

100

101

1-4 Vol. 3A

ABOUT THIS MANUAL

Chapter 25 — Virtual-Machine Monitoring Programming Considerations. Describes

programming considerations for VMMs. VMMs manage virtual machines (VMs).

Chapter 26 — Virtualization of System Resources. Describes the virtualization of the system

resources. These include: debugging facilities, address translation, physical memory, and micro-

code update facilities.

Chapter 27 — Handling Boundary Conditions in a Virtual Machine Monitor. Describes

what a VMM must consider when handling exceptions, interrupts, error conditions, and transi-

tions between activity states.

Appendix A — Performance-Monitoring Events. Lists the events that can be counted with

the performance-monitoring counters and the codes used to select these events. Both Pentium

processor and P6 family processor events are described.

Appendix B — Model-Specific Registers (MSRs). Lists the MSRs available in the Pentium

processors, the P6 family processors, and the Pentium 4 and Intel Xeon processors and describes

their functions.

Appendix C — MP Initialization For P6 Family Processors. Gives an example of how to use

of the MP protocol to boot P6 family processors in n MP system.

Appendix D — Programming the LINT0 and LINT1 Inputs. Gives an example of how to

program the LINT0 and LINT1 pins for specific interrupt vectors.

Appendix E — Interpreting Machine-Check Error Codes. Gives an example of how to inter-

pret the error codes for a machine-check error that occurred on a P6 family processor.

Appendix F — APIC Bus Message Formats. Describes the message formats for messages

transmitted on the APIC bus for P6 family and Pentium processors.

Appendix G — VMX Capability Reporting Facility. Describes the VMX capability MSRs.

Support for specific VMX features is determined by reading capability MSRs.

Appendix H — Field Encoding in VMCS. Enumerates all fields in the VMCS and their encod-

ings. Fields are grouped by width (16-bit, 32-bit, etc.) and type (guest-state, host-state, etc.).

Appendix I — VM Basic Exit Reasons. Describes the 32-bit fields that encode reasons for a

VM-Exit. Examples of exit reasons include, but are not limited to: software interrupts, processor

exceptions, software traps, NMIs, external interrupts, and triple faults.

Appendix J — VM Instruction Error Numbers. Describes the VM-instruction error codes

generated by failed VM instruction executions (that have a valid working-VMCS pointer).

1.3 NOTATIONAL CONVENTIONS

This manual uses specific notation for data-structure formats, for symbolic representation of

instructions, and for hexadecimal and binary numbers. A review of this notation makes the

manual easier to read.

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 635 636

Comments to this Manuals

No comments

Intel ARCHITECTURE IA-32 User Manual Page 40

Comments to this Manuals

Related products and manuals for Processors Intel ARCHITECTURE IA-32