Intel ARCHITECTURE IA-32 User Manual download pdf (Page 494)

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11-6 Vol. 3A

INTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING

• Other exceptions can occur indirectly due to the faulty execution of the exception handlers

for the above exceptions.

11.5.1 Effect of MMX Instructions on Pending x87 Floating-Point

Exceptions

If an x87 FPU floating-point exception is pending and the processor encounters an MMX

instruction, the processor generates a x87 FPU floating-point error (#MF) prior to executing the

MMX instruction, to allow the pending exception to be handled by the x87 FPU floating-point

error exception handler. While this exception handler is executing, the x87 FPU state is main-

tained and is visible to the handler. Upon returning from the exception handler, the MMX

instruction is executed, which will alter the x87 FPU state, as described in Section 11.2, “The

MMX State and MMX Register Aliasing.”

11.6 DEBUGGING MMX CODE

The debug facilities of the IA-32 architecture operate in the same manner when executing MMX

instructions as when executing other IA-32 architecture instructions.

To correctly interpret the contents of the MMX or x87 FPU registers from the FSAVE/FNSAVE

or FXSAVE image in memory, a debugger needs to take account of the relationship between the

x87 FPU register’s logical locations relative to TOS and the MMX register’s physical locations.

In the x87 FPU context, STn refers to an x87 FPU register at location n relative to the TOS.

However, the tags in the x87 FPU tag word are associated with the physical locations of the x87

FPU registers (R0 through R7). The MMX registers always refer to the physical locations of the

registers (with MM0 through MM7 being mapped to R0 through R7). Figure 11-2 shows this

relationship. Here, the inner circle refers to the physical location of the x87 FPU and MMX

registers. The outer circle refers to the x87 FPU registers’s relative location to the current TOS.

When the TOS equals 0 (case A in Figure 11-2), ST0 points to the physical location R0 on the

floating-point stack. MM0 maps to ST0, MM1 maps to ST1, and so on.

When the TOS equals 2 (case B in Figure 11-2), ST0 points to the physical location R2. MM0

maps to ST6, MM1 maps to ST7, MM2 maps to ST0, and so on.

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