Intel ARCHITECTURE IA-32 User Manual download pdf (Page 100)

3-20 Vol. 3A

PROTECTED-MODE MEMORY MANAGEMENT

3.5.2 Segment Descriptor Tables in IA-32e Mode

In IA-32e mode, a segment descriptor table can contain up to 8192 (2

) 8-byte descriptors. An

entry in the segment descriptor table can be 8 bytes. System descriptors are expanded to 16 bytes

(occupying the space of two entries).

GDTR and LDTR registers are expanded to hold 64-bit base address. The corresponding

pseudo-descriptor is 80 bits. (see the bottom diagram in Figure 3-11).

The following system descriptors expand to 16 bytes:

— Call gate descriptors (see Section 4.8.3.1, “IA-32e Mode Call Gates”)

— IDT gate descriptors (see Section 5.14.1, “64-Bit Mode IDT”)

— LDT and TSS descriptors (see Section 6.2.3, “TSS Descriptor in 64-bit mode”).

3.6 PAGING (VIRTUAL MEMORY) OVERVIEW

When operating in protected mode, IA-32 architecture permits linear address space to be

mapped directly into a large physical memory (for example, 4 GBytes of RAM) or indirectly

(using paging) into a smaller physical memory and disk storage. This latter method of mapping

the linear address space is referred to as virtual memory or demand-paged virtual memory.

When paging is used, the processor divides the linear address space into fixed-size pages (of

4 KBytes, 2 MBytes, or 4 MBytes in length) that can be mapped into physical memory and/or

disk storage. When a program (or task) references a logical address in memory, the processor

translates the address into a linear address and then uses its paging mechanism to translate the

linear address into a corresponding physical address.

If the page containing the linear address is not currently in physical memory, the processor

generates a page-fault exception (#PF). The exception handler for the page-fault exception typi-

cally directs the operating system or executive to load the page from disk storage into physical

memory (perhaps writing a different page from physical memory out to disk in the process).

When the page has been loaded in physical memory, a return from the exception handler causes

the instruction that generated the exception to be restarted. The information that the processor

uses to map linear addresses into the physical address space and to generate page-fault excep-

tions (when necessary) is contained in page directories and page tables stored in memory.

Paging is different from segmentation through its use of fixed-size pages. Unlike segments,

which usually are the same size as the code or data structures they hold, pages have a fixed size.

If segmentation is the only form of address translation used, a data structure present in physical

memory will have all of its parts in memory. If paging is used, a data structure can be partly in

memory and partly in disk storage.

To minimize the number of bus cycles required for address translation, the most recently

accessed page-directory and page-table entries are cached in the processor in devices called

translation lookaside buffers (TLBs). The TLBs satisfy most requests for reading the current

page directory and page tables without requiring a bus cycle. Extra bus cycles occur only when

the TLBs do not contain a page-table entry, which typically happens when a page has not been

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Intel ARCHITECTURE IA-32 User Manual Page 100