Intel ARCHITECTURE IA-32 User Manual download pdf (Page 64)

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2-16 Vol. 3A

SYSTEM ARCHITECTURE OVERVIEW

2.4.3 IDTR Interrupt Descriptor Table Register

The IDTR register holds the base address (32 bits in protected mode; 64 bits in IA-32e mode)

and 16-bit table limit for the IDT. The base address specifies the linear address of byte 0 of the

IDT; the table limit specifies the number of bytes in the table. The LIDT and SIDT instructions

load and store the IDTR register, respectively. On power up or reset of the processor, the base

address is set to the default value of 0 and the limit is set to 0FFFFH. The base address and limit

in the register can then be changed as part of the processor initialization process.

See also: Section 5.10, “Interrupt Descriptor Table (IDT).”

2.4.4 Task Register (TR)

The task register holds the 16-bit segment selector, base address (32 bits in protected mode; 64

bits in IA-32e mode), segment limit, and descriptor attributes for the TSS of the current task.

The selector references the TSS descriptor in the GDT. The base address specifies the linear

address of byte 0 of the TSS; the segment limit specifies the number of bytes in the TSS. See

also: Section 6.2.4, “Task Register.”

The LTR and STR instructions load and store the segment selector part of the task register,

respectively. When the LTR instruction loads a segment selector in the task register, the base

address, limit, and descriptor attributes from the TSS descriptor are automatically loaded into

the task register. On power up or reset of the processor, the base address is set to the default

value of 0 and the limit is set to 0FFFFH.

When a task switch occurs, the task register is automatically loaded with the segment selector

and descriptor for the TSS for the new task. The contents of the task register are not automati-

cally saved prior to writing the new TSS information into the register.

2.5 CONTROL REGISTERS

Control registers (CR0, CR1, CR2, CR3, and CR4; see Figure 2-6) determine operating mode

of the processor and the characteristics of the currently executing task. These registers are 32

bits in all 32-bit modes and compatibility mode.

In 64-bit mode, control registers are expanded to 64 bits. The MOV CRn instructions are used

to manipulate the register bits. Operand-size prefixes for these instructions are ignored. The

following is also true:

• Bits 63:32 of CR0 and CR4 are reserved and must be written with zeros. Writing a nonzero

value to any of the upper 32 bits results in a general-protection exception, #GP(0).

• All 64 bits of CR2 are writable by software.

• Bits 51:40 of CR3 are reserved and must be 0.

• The MOV CRn instructions do not check that addresses written to CR2 and CR3 are within

the linear-address or physical-address limitations of the implementation.

• Register CR8 is available in 64-bit mode only.

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