Intel ARCHITECTURE IA-32 User Manual download pdf (Page 282)

7-14 Vol. 3A

MULTIPLE-PROCESSOR MANAGEMENT

7.4 SERIALIZING INSTRUCTIONS

The IA-32 architecture defines several serializing instructions. These instructions force the

processor to complete all modifications to flags, registers, and memory by previous instructions

and to drain all buffered writes to memory before the next instruction is fetched and executed.

For example, when a MOV to control register instruction is used to load a new value into control

before it enters protected mode. This serializing operation insures that all operations that were

started while the processor was in real-address mode are completed before the switch to

protected mode is made.

The concept of serializing instructions was introduced into the IA-32 architecture with the

Pentium processor to support parallel instruction execution. Serializing instructions have no

meaning for the Intel486 and earlier processors that do not implement parallel instruction execu-

tion.

It is important to note that executing of serializing instructions on Pentium 4, Intel Xeon, and P6

family processors constrain speculative execution because the results of speculatively executed

instructions are discarded. The following instructions are serializing instructions:

• Privileged serializing instructions — MOV (to control register, with the exception of

MOV CR8

), MOV (to debug register), WRMSR, INVD, INVLPG, WBINVD, LGDT,

LLDT, LIDT, and LTR.

• Non-privileged serializing instructions — CPUID, IRET, and RSM.

When the processor serializes instruction execution, it ensures that all pending memory transac-

tions are completed (including writes stored in its store buffer) before it executes the next

instruction. Nothing can pass a serializing instruction and a serializing instruction cannot pass

any other instruction (read, write, instruction fetch, or I/O). For example, CPUID can be

executed at any privilege level to serialize instruction execution with no effect on program flow,

except that the EAX, EBX, ECX, and EDX registers are modified.

The following instructions are memory ordering instructions, not serializing instructions. These

drain the data memory subsystem. They do not effect the instruction execution stream:

• Non-privileged memory ordering instructions — SFENCE, LFENCE, and MFENCE.

The SFENCE, LFENCE, and MFENCE instructions provide more granularity in controlling the

serialization of memory loads and stores (see Section 7.2.4, “Strengthening or Weakening the

Memory Ordering Model”).

The following additional information is worth noting regarding serializing instructions:

• The processor does not writeback the contents of modified data in its data cache to external

memory when it serializes instruction execution. Software can force modified data to be

written back by executing the WBINVD instruction, which is a serializing instruction. It

should be noted that frequent use of the WBINVD instruction will seriously reduce system

performance.

1. MOV CR8 is not defined architecturally as a serializing instruction.

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Intel ARCHITECTURE IA-32 User Manual Page 282