Intel ARCHITECTURE IA-32 User Manual download pdf (Page 53)

Vol. 3A 2-5

SYSTEM ARCHITECTURE OVERVIEW

2.1.1 Global and Local Descriptor Tables

When operating in protected mode, all memory accesses pass through either the global

descriptor table (GDT) or an optional local descriptor table (LDT) as shown in Figure 2-1. These

tables contain entries called segment descriptors. Segment descriptors provide the base address

of segments well as access rights, type, and usage information.

Each segment descriptor has an associated segment selector. A segment selector provides the

software that uses it with an index into the GDT or LDT (the offset of its associated segment

descriptor), a global/local flag (determines whether the selector points to the GDT or the LDT),

and access rights information.

To access a byte in a segment, a segment selector and an offset must be supplied. The segment

selector provides access to the segment descriptor for the segment (in the GDT or LDT). From

the segment descriptor, the processor obtains the base address of the segment in the linear

address space. The offset then provides the location of the byte relative to the base address. This

mechanism can be used to access any valid code, data, or stack segment, provided the segment

is accessible from the current privilege level (CPL) at which the processor is operating. The CPL

is defined as the protection level of the currently executing code segment.

See Figure 2-1. The solid arrows in the figure indicate a linear address, dashed lines indicate a

segment selector, and the dotted arrows indicate a physical address. For simplicity, many of the

segment selectors are shown as direct pointers to a segment. However, the actual path from a

segment selector to its associated segment is always through a GDT or LDT.

The linear address of the base of the GDT is contained in the GDT register (GDTR); the linear

address of the LDT is contained in the LDT register (LDTR).

2.1.1.1 Global and Local Descriptor Tables in IA-32 Mode

GDTR and LDTR registers are expanded to 64-bit wide in both IA-32e sub-modes (64-bit mode

and compatibility mode). For more information: see Section 3.5.2, “Segment Descriptor Tables

in IA-32e Mode.”

Global and local descriptor tables are expanded in 64-bit mode to support 64-bit base addresses,

(16-byte LDT descriptors hold a 64-bit base address and various attributes). In compatibility

mode, descriptors are not expanded.

2.1.2 System Segments, Segment Descriptors, and Gates

Besides code, data, and stack segments that make up the execution environment of a program or

procedure, the architecture defines two system segments: the task-state segment (TSS) and the

LDT. The GDT is not considered a segment because it is not accessed by means of a segment

selector and segment descriptor. TSSs and LDTs have segment descriptors defined for them.

The architecture also defines a set of special descriptors called gates (call gates, interrupt gates,

trap gates, and task gates). These provide protected gateways to system procedures and handlers

that may operate at a different privilege level than application programs and most procedures.

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Intel ARCHITECTURE IA-32 User Manual Page 53