Intel ARCHITECTURE IA-32 User Manual download pdf (Page 630)

17-38 Vol. 3A

IA-32 ARCHITECTURE COMPATIBILITY

way of ensuring ordering between routines that produce weakly-ordered results and routines that

consume this data.

No re-ordering of reads occurs on the Pentium processor, except under the condition noted in

Section 7.2.1, “Memory Ordering in the Intel® Pentium® and Intel486™ Processors,” and in

the following paragraph describing the Intel486 processor.

Specifically, the store buffers are flushed before the IN instruction is executed. No reads (as a

result of cache miss) are reordered around previously generated writes sitting in the store

buffers. The implication of this is that the store buffers will be flushed or emptied before a subse-

quent bus cycle is run on the external bus.

On both the Intel486 and Pentium processors, under certain conditions, a memory read will go

onto the external bus before the pending memory writes in the buffer even though the writes

occurred earlier in the program execution. A memory read will only be reordered in front of all

writes pending in the buffers if all writes pending in the buffers are cache hits and the read is a

cache miss. Under these conditions, the Intel486 and Pentium processors will not read from an

external memory location that needs to be updated by one of the pending writes.

During a locked bus cycle, the Intel486 processor will always access external memory, it will

never look for the location in the on-chip cache. All data pending in the Intel486 processor's

store buffers will be written to memory before a locked cycle is allowed to proceed to the

external bus. Thus, the locked bus cycle can be used for eliminating the possibility of reordering

read cycles on the Intel486 processor. The Pentium processor does check its cache on a read-

modify-write access and, if the cache line has been modified, writes the contents back to

memory before locking the bus. The P6 family processors write to their cache on a read-modify-

write operation (if the access does not split across a cache line) and does not write back to system

memory. If the access does split across a cache line, it locks the bus and accesses system

memory.

I/O reads are never reordered in front of buffered memory writes on an IA-32 processor. This

ensures an update of all memory locations before reading the status from an I/O device.

17.34. BUS LOCKING

The Intel 286 processor performs the bus locking differently than the Intel P6 family, Pentium,

Intel486, and Intel386 processors. Programs that use forms of memory locking specific to the

Intel 286 processor may not run properly when run on later processors.

A locked instruction is guaranteed to lock only the area of memory defined by the destination

operand, but may lock a larger memory area. For example, typical 8086 and Intel 286 configu-

rations lock the entire physical memory space. Programmers should not depend on this.

On the Intel 286 processor, the LOCK prefix is sensitive to IOPL. If the CPL is greater than the

IOPL, a general-protection exception (#GP) is generated. On the Intel386 DX, Intel486, and

Pentium, and P6 family processors, no check against IOPL is performed.

The Pentium processor automatically asserts the LOCK# signal when acknowledging external

interrupts. After signaling an interrupt request, an external interrupt controller may use the data

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Intel ARCHITECTURE IA-32 User Manual Page 630