Intel ARCHITECTURE IA-32 User Manual download pdf (Page 297)

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Vol. 3A 7-29

MULTIPLE-PROCESSOR MANAGEMENT

of memory, independent of the processor on which it is running. See Section 10.11, “Memory

Type Range Registers (MTRRs),” for information on setting up MTRRs.

7.8.4 Page Attribute Table (PAT)

Each logical processor has its own PAT MSR (IA32_CR_PAT). However, as described in

Section 10.12, “Page Attribute Table (PAT),” the PAT MSR settings must be the same for all

processors in a system, including the logical processors.

7.8.5 Machine Check Architecture

In the HT Technology context, all of the machine check architecture (MCA) MSRs (except for

the IA32_MCG_STATUS and IA32_MCG_CAP MSRs) are duplicated for each logical

processor. This permits logical processors to initialize, configure, query, and handle machine-

check exceptions simultaneously within the same physical processor. The design is compatible

with machine check exception handlers that follow the guidelines given in Chapter 14,

“Machine-Check Architecture.”

The IA32_MCG_STATUS MSR is duplicated for each logical processor so that its machine

check in progress bit field (MCIP) can be used to detect recursion on the part of MCA handlers.

In addition, the MSR allows each logical processor to determine that a machine-check exception

is in progress independent of the actions of another logical processor in the same physical

package.

Because the logical processors within a physical package are tightly coupled with respect to

shared hardware resources, both logical processors are notified of machine check errors that

occur within a given physical processor. If machine-check exceptions are enabled when a fatal

error is reported, all the logical processors within a physical package are dispatched to the

machine-check exception handler. If machine-check exceptions are disabled, the logical proces-

sors enter the shutdown state and assert the IERR# signal.

When enabling machine-check exceptions, the MCE flag in control register CR4 should be set

for each logical processor.

7.8.6 Debug Registers and Extensions

Each logical processor has its own set of debug registers (DR0, DR1, DR2, DR3, DR6, DR7)

and its own debug control MSR. These can be set to control and record debug information for

each logical processor independently. Each logical processor also has its own last branch records

(LBR) stack.

7.8.7 Performance Monitoring Counters

Performance counters and their companion control MSRs are shared between the logical proces-

sors within the physical processor. As a result, software must manage the use of these resources.

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