Intel ARCHITECTURE IA-32 User Manual download pdf (Page 450)

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10-10 Vol. 3A

MEMORY CACHE CONTROL

For a description of these instructions and there intended use, see Section 10.5.5, “Cache

Management Instructions.”

10.4 CACHE CONTROL PROTOCOL

The following section describes the cache control protocol currently defined for the IA-32 archi-

tecture. This protocol is used by the Pentium 4, Intel Xeon, P6 family, and Pentium processors.

In the L1 data cache and in the L2 and L3 unified caches, the MESI (modified, exclusive, shared,

invalid) cache protocol maintains consistency with caches of other processors. The L1 data

cache and the L2 and L3 unified caches have two MESI status flags per cache line. Each line

can thus be marked as being in one of the states defined in Table 10-4. In general, the operation

of the MESI protocol is transparent to programs.

The L1 instruction cache in P6 family processors implements only the “SI” part of the MESI

protocol, because the instruction cache is not writable. The instruction cache monitors changes

in the data cache to maintain consistency between the caches when instructions are modified.

See Section 10.6, “Self-Modifying Code,” for more information on the implications of caching

instructions.

10.5 CACHE CONTROL

The IA-32 architecture provides a variety of mechanisms for controlling the caching of data and

instructions and for controlling the ordering of reads and writes between the processor, the

caches, and memory. These mechanisms can be divided into two groups:

• Cache control registers and bits — The IA-32 architecture defines several dedicated

registers and various bits within control registers and page- and directory-table entries that

control the caching system memory locations in the L1, L2, and L3 caches. These

mechanisms control the caching of virtual memory pages and of regions of physical

memory.

Table 10-4. MESI Cache Line States

Cache Line State M (Modified) E (Exclusive) S (Shared) I (Invalid)

This cache line is valid? Yes Yes Yes No

The memory copy is… Out of date Valid Valid —

Copies exist in caches of

other processors?

No No Maybe Maybe

A write to this line … Does not go to

the system bus.

Does not go to

the system bus.

Causes the

processor to

gain exclusive

ownership of the

line.

Goes directly to

the system bus.

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