Intel ARCHITECTURE IA-32 User Manual download pdf (Page 462)

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10-22 Vol. 3A

MEMORY CACHE CONTROL

For Intel486 processors, a write to an instruction in the cache will modify it in both the cache

and memory, but if the instruction was prefetched before the write, the old version of the instruc-

tion could be the one executed. To prevent the old instruction from being executed, flush the

instruction prefetch unit by coding a jump instruction immediately after any write that modifies

an instruction.

10.7 IMPLICIT CACHING (PENTIUM 4, INTEL XEON,

AND P6 FAMILY PROCESSORS)

Implicit caching occurs when a memory element is made potentially cacheable, although the

element may never have been accessed in the normal von Neumann sequence. Implicit caching

occurs on the Pentium 4, Intel Xeon, and P6 family processors due to aggressive prefetching,

branch prediction, and TLB miss handling. Implicit caching is an extension of the behavior of

existing Intel386, Intel486, and Pentium processor systems, since software running on these

processor families also has not been able to deterministically predict the behavior of instruction

prefetch.

To avoid problems related to implicit caching, the operating system must explicitly invalidate

the cache when changes are made to cacheable data that the cache coherency mechanism does

not automatically handle. This includes writes to dual-ported or physically aliased memory

boards that are not detected by the snooping mechanisms of the processor, and changes to page-

table entries in memory.

The code in Example 10-13 shows the effect of implicit caching on page-table entries. The linear

address F000H points to physical location B000H (the page-table entry for F000H contains the

value B000H), and the page-table entry for linear address F000 is PTE_F000.

Example 10-13. Effect of Implicit Caching on Page-Table Entries

mov EAX, CR3 ; Invalidate the TLB

mov CR3, EAX ; by copying CR3 to itself

mov PTE_F000, A000H; Change F000H to point to A000H

mov EBX, [F000H];

Because of speculative execution in the Pentium 4, Intel Xeon, and P6 family processors, the

last MOV instruction performed would place the value at physical location B000H into EBX,

rather than the value at the new physical address A000H. This situation is remedied by placing

a TLB invalidation between the load and the store.

10.8 EXPLICIT CACHING

The Pentium III processor introduced four new instructions, the PREFETCHh instructions, that

provide software with explicit control over the caching of data. These instructions provide

“hints” to the processor that the data requested by a PREFETCHh instruction should be read into

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