Intel ARCHITECTURE IA-32 User Manual download pdf (Page 317)

Vol. 3A 7-49

MULTIPLE-PROCESSOR MANAGEMENT

These above two values bear no relationship to cache line size in the system and software should

not make any assumptions to that effect. Within a single-cluster system, the two parameters

should default to be the same (the size of the monitor triggering area is the same as the system

coherence line size).

Based on the monitor line sizes returned by the CPUID, the OS should dynamically allocate

structures with appropriate padding. If static data structures must be used by an OS, attempt to

adapt the data structure and use a dynamically allocated data buffer for thread synchronization.

When the latter technique is not possible, consider not using MONITOR/MWAIT when using

static data structures.

To set up the data structure correctly for MONITOR/MWAIT on multi-clustered systems: inter-

action between processors, chipsets, and the BIOS is required (system coherence line size may

depend on the chipset used in the system; the size could be different from the processor’s

monitor triggering area). The BIOS is responsible to set the correct value for system coherence

line size using the IA32_MONITOR_FILTER_LINE_SIZE MSR. Depending on the relative

magnitude of the size of the monitor triggering area versus the value written into the

IA32_MONITOR_FILTER_LINE_SIZE MSR, the smaller of the parameters will be reported

as the Smallest Monitor Line Size. The larger of the parameters will be reported as the Largest

Monitor Line Size.

7.11.6 Required Operating System Support

This section describes changes that must be made to an operating system to run on IA-32 proces-

sors supporting Hyper-Threading Technology. It also describes optimizations that can help an

operating system make more efficient use of the logical processors sharing execution resources.

The required changes and suggested optimizations are representative of the types of modifica-

tions that appear in Windows XP and Linux kernel 2.4.0 operating systems for IA-32 processors

supporting Hyper-Threading Technology. Additional optimizations for IA-32 processors

supporting Hyper-Threading Technology are described in the IA-32 Intel® Architecture Optimi-

zation Reference Manual.

7.11.6.1 Use the PAUSE Instruction in Spin-Wait Loops

Intel recommends that a PAUSE instruction be placed in all spin-wait loops that run on Intel

Xeon, Pentium 4 processors and dual-core processors.

Software routines that use spin-wait loops include multiprocessor synchronization primitives

(spin-locks, semaphores, and mutex variables) and idle loops. Such routines keep the processor

core busy executing a load-compare-branch loop while a thread waits for a resource to become

available. Including a PAUSE instruction in such a loop greatly improves efficiency (see

Section 7.11.2, “PAUSE Instruction”). The following routine gives an example of a spin-wait

loop that uses a PAUSE instruction:

Spin_Lock:

CMP lockvar, 0;Check if lock is free

JE Get_Lock

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Intel ARCHITECTURE IA-32 User Manual Page 317