Intel ARCHITECTURE IA-32 User Manual download pdf (Page 356)

8-32 Vol. 3A

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

Here, the TPR value is the task priority value in the TPR (see Figure 8-18), the IRRV value is

the vector number for the highest priority bit that is set in the IRR (see Figure 8-20) or 00H (if

no IRR bit is set), and the ISRV value is the vector number for the highest priority bit that is set

in the ISR (see Figure 8-20). Following arbitration among the destination processors, the

processor with the lowest value in its APR handles the IPI and the other processors ignore it.

(P6 family and Pentium processors.) For these processors, if a focus processor exists, it may

accept the interrupt, regardless of its priority. A processor is said to be the focus of an interrupt

if it is currently servicing that interrupt or if it has a pending request for that interrupt. For Intel

Xeon processors, the concept of a focus processor is not supported.

In operating systems that use the lowest priority delivery mode but do not update the TPR, the

TPR information saved in the chipset will potentially cause the interrupt to be always delivered

to the same processor from the logical set. This behavior is functionally backward compatible

with the P6 family processor but may result in unexpected performance implications.

8.6.3 IPI Delivery and Acceptance

When the low double-word of the ICR is written to, the local APIC creates an IPI message from

the information contained in the ICR and sends the message out on the system bus (Pentium 4

and Intel Xeon processors) or the APIC bus (P6 family and Pentium processors). The manner in

which these IPIs are handled after being issues in described in Section 8.8, “Handling Interrupts.”

8.7 SYSTEM AND APIC BUS ARBITRATION

When several local APICs and the I/O APIC are sending IPI and interrupt messages on the

system bus (or APIC bus), the order in which the messages are sent and handled is determined

through bus arbitration.

For the Pentium 4 and Intel Xeon processors, the local and I/O APICs use the arbitration mech-

anism defined for the system bus to determine the order in which IPIs are handled. This mech-

anism is non-architectural and cannot be controlled by software.

For the P6 family and Pentium processors, the local and I/O APICs use an APIC-based arbitra-

tion mechanism to determine the order in which IPIs are handled. Here, each local APIC is given

an arbitration priority of from 0 to 15, which the I/O APIC uses during arbitration to determine

which local APIC should be given access to the APIC bus. The local APIC with the highest arbi-

tration priority always wins bus access. Upon completion of an arbitration round, the winning

local APIC lowers its arbitration priority to 0 and the losing local APICs each raise theirs by 1.

The current arbitration priority for a local APIC is stored in a 4-bit, software-transparent arbi-

tration ID (Arb ID) register. During reset, this register is initialized to the APIC ID number

(stored in the local APIC ID register). The INIT level-deassert IPI, which is issued with and ICR

command, can be used to resynchronize the arbitration priorities of the local APICs by resetting

Arb ID register of each agent to its current APIC ID value. (The Pentium 4 and Intel Xeon

processors do not implement the Arb ID register.)

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Intel ARCHITECTURE IA-32 User Manual Page 356