Intel ARCHITECTURE IA-32 User Manual download pdf (Page 183)

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INTERRUPT AND EXCEPTION HANDLING

For trap-class exceptions, the return instruction pointer points to the instruction following the

trapping instruction. If a trap is detected during an instruction which transfers execution, the

return instruction pointer reflects the transfer. For example, if a trap is detected while executing

a JMP instruction, the return instruction pointer points to the destination of the JMP instruction,

not to the next address past the JMP instruction. All trap exceptions allow program or task restart

with no loss of continuity. For example, the overflow exception is a trap exception. Here, the

return instruction pointer points to the instruction following the INTO instruction that tested

EFLAGS.OF (overflow) flag. The trap handler for this exception resolves the overflow condi-

tion. Upon return from the trap handler, program or task execution continues at the instruction

following the INTO instruction.

The abort-class exceptions do not support reliable restarting of the program or task. Abort

handlers are designed to collect diagnostic information about the state of the processor when the

abort exception occurred and then shut down the application and system as gracefully as

possible.

Interrupts rigorously support restarting of interrupted programs and tasks without loss of conti-

nuity. The return instruction pointer saved for an interrupt points to the next instruction to be

executed at the instruction boundary where the processor took the interrupt. If the instruction

just executed has a repeat prefix, the interrupt is taken at the end of the current iteration with the

registers set to execute the next iteration.

The ability of a P6 family processor to speculatively execute instructions does not affect the

taking of interrupts by the processor. Interrupts are taken at instruction boundaries located

during the retirement phase of instruction execution; so they are always taken in the “in-order”

instruction stream. See Chapter 2, “IA-32 Intel® Architecture,” in the IA-32 Intel® Architecture

Software Developer’s Manual, Volume 1, for more information about the P6 family processors’

microarchitecture and its support for out-of-order instruction execution.

Note that the Pentium processor and earlier IA-32 processors also perform varying amounts of

prefetching and preliminary decoding. With these processors as well, exceptions and interrupts

are not signaled until actual “in-order” execution of the instructions. For a given code sample,

the signaling of exceptions occurs uniformly when the code is executed on any family of IA-32

processors (except where new exceptions or new opcodes have been defined).

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