Intel ARCHITECTURE IA-32 User Manual download pdf (Page 73)

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Vol. 3A 2-25

SYSTEM ARCHITECTURE OVERVIEW

2.6.1 Loading and Storing System Registers

The GDTR, LDTR, IDTR, and TR registers each have a load and store instruction for loading

data into and storing data from the register:

• LGDT (Load GDTR Register) — Loads the GDT base address and limit from memory

into the GDTR register.

• SGDT (Store GDTR Register) — Stores the GDT base address and limit from the GDTR

• LIDT (Load IDTR Register) — Loads the IDT base address and limit from memory into

the IDTR register.

• SIDT (Load IDTR Register — Stores the IDT base address and limit from the IDTR

• LLDT (Load LDT Register) — Loads the LDT segment selector and segment descriptor

from memory into the LDTR. (The segment selector operand can also be located in a

general-purpose register.)

MOV DRn Load and store debug registers No Yes

INVD Invalidate cache, no writeback No Yes

WBINVD Invalidate cache, with writeback No Yes

INVLPG Invalidate TLB entry No Yes

HLT Halt Processor No Yes

LOCK (Prefix) Bus Lock Yes No

RSM Return from system management mode No Yes

RDMSR

Read Model-Specific Registers No Yes

WRMSR

Write Model-Specific Registers No Yes

RDPMC

Read Performance-Monitoring Counter Yes Yes

RDTSC

Read Time-Stamp Counter Yes Yes

NOTES:

1. Useful to application programs running at a CPL of 1 or 2.

2. The TSD and PCE flags in control register CR4 control access to these instructions by application

programs running at a CPL of 3.

3. These instructions were introduced into the IA-32 Architecture with the Pentium processor.

4. This instruction was introduced into the IA-32 Architecture with the Pentium Pro processor and the

Pentium processor with MMX technology.

5. This instruction is not supported in 64-bit mode.

Table 2-2. Summary of System Instructions (Contd.)

Instruction Description

Useful to

Application?

Protected from

Application?

1 2 ... 68 69 70 71 72 73 74 75 76 77 78 ... 635 636

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