Intel ARCHITECTURE IA-32 User Manual download pdf (Page 125)

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Vol. 3A 3-45

PROTECTED-MODE MEMORY MANAGEMENT

3.11 MAPPING SEGMENTS TO PAGES

The segmentation and paging mechanisms provide in the IA-32 architecture support a wide

variety of approaches to memory management. When segmentation and paging is combined,

segments can be mapped to pages in several ways. To implement a flat (unsegmented)

addressing environment, for example, all the code, data, and stack modules can be mapped to

one or more large segments (up to 4-GBytes) that share same range of linear addresses (see

Figure 3-2). Here, segments are essentially invisible to applications and the operating-system or

executive. If paging is used, the paging mechanism can map a single linear address space

(contained in a single segment) into virtual memory. Or, each program (or task) can have its own

large linear address space (contained in its own segment), which is mapped into virtual memory

through its own page directory and set of page tables.

Segments can be smaller than the size of a page. If one of these segments is placed in a page

which is not shared with another segment, the extra memory is wasted. For example, a small data

structure, such as a 1-byte semaphore, occupies 4K bytes if it is placed in a page by itself. If

many semaphores are used, it is more efficient to pack them into a single page.

The IA-32 architecture does not enforce correspondence between the boundaries of pages and

segments. A page can contain the end of one segment and the beginning of another. Likewise, a

segment can contain the end of one page and the beginning of another.

Memory-management software may be simpler and more efficient if it enforces some alignment

between page and segment boundaries. For example, if a segment which can fit in one page is

placed in two pages, there may be twice as much paging overhead to support access to that

segment.

One approach to combining paging and segmentation that simplifies memory-management soft-

ware is to give each segment its own page table, as shown in Figure 3-28. This convention gives

the segment a single entry in the page directory which provides the access control information

for paging the entire segment.

64-bit 4-KByte and 2-MByte pages (PAE

= 1, PSE = x)

PML4E Bit [63], bits [51:40]

4-KByte and 2-MByte pages (PAE

= 1, PSE = x)

PDPTE Bit [63], bits [51:40]

2-MByte page (PAE = 1, PSE = x) PDE, 2-MByte page Bit [63], bits [51:40] & [20:13]

4-KByte pages (PAE = 1, PSE = x) PDE, 4-KByte page Bit [63], bits [51:40]

4-KByte and 2-MByte pages (PAE

= 1, PSE = x)

PTE Bit [63], bits [51:40]

NOTE:

x = Bit does not impact behavior.

Table 3-5. Reserved Bit Checking When Execute Disable Bit is Enabled (Contd.)

Mode Paging Mode Paging Structure Check Bits

1 2 ... 120 121 122 123 124 125 126 127 128 129 130 ... 635 636

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Intel ARCHITECTURE IA-32 User Manual Page 125

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