Intel ARCHITECTURE IA-32 User Manual download pdf (Page 533)

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Vol. 3A 14-7

MACHINE-CHECK ARCHITECTURE

where the error occurred. Do not read these registers if they are not implemented in the

processor.

• MISCV (IA32_MCi_MISC register valid) flag, bit 59 — Indicates (when set) that the

IA32_MCi_MISC register contains additional information regarding the error. When clear,

this flag indicates that the IA32_MCi_MISC register is either not implemented or does not

contain additional information regarding the error. Do not read these registers if they are

not implemented in the processor.

• EN (error enabled) flag, bit 60 — Indicates (when set) that the error was enabled by the

associated EEj bit of the IA32_MCi_CTL register.

• UC (error uncorrected) flag, bit 61 — Indicates (when set) that the processor did not or

was not able to correct the error condition. When clear, this flag indicates that the

processor was able to correct the error condition.

• OVER (machine check overflow) flag, bit 62 — Indicates (when set) that a machine-

check error occurred while the results of a previous error were still in the error-reporting

The processor sets the OVER flag and software is responsible for clearing it. Enabled

errors are written over disabled errors, and uncorrected errors are written over corrected

errors. Uncorrected errors are not written over previous valid uncorrected errors.

• VAL (IA32_MCi_STATUS register valid) flag, bit 63 — Indicates (when set) that the

information within the IA32_MCi_STATUS register is valid. When this flag is set, the

processor follows the rules given for the OVER flag in the IA32_MCi_STATUS register

when overwriting previously valid entries. The processor sets the VAL flag and software is

responsible for clearing it.

14.3.2.3 IA32_MCi_ADDR MSRs

The IA32_MCi_ADDR MSR (called MCi_ADDR in the P6 family processors) contains the

address of the code or data memory location that produced the machine-check error if the

ADDRV flag in the IA32_MCi_STATUS register is set (see Section 14-7, “IA32_MCi_ADDR

MSR”). The IA32_MCi_ADDR register is either not implemented or contains no address if the

ADDRV flag in the IA32_MCi_STATUS register is clear. When not implemented in the

processor, all reads and writes to this MSR will cause a general protection exception.

The address returned is an offset into a segment, linear address, or physical address. This

depends on the error encountered. These registers can be cleared by explicitly writing 0s to bits

that are not reserved. Writing 1s to these registers will cause a general-protection exception. See

Figure 14-7.

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