Intel ARCHITECTURE IA-32 User Manual download pdf (Page 269)

100

101

Vol. 3A 7-1

CHAPTER 7

MULTIPLE-PROCESSOR MANAGEMENT

The IA-32 architecture provides several mechanisms for managing and improving the perfor-

mance of multiple processors connected to the same system bus. These mechanisms include:

• Bus locking and/or cache coherency management for performing atomic operations on

system memory.

• Serializing instructions. These instructions apply only to the Pentium 4, Intel Xeon, P6

family, and Pentium processors.

• An advance programmable interrupt controller (APIC) located on the processor chip (see

Chapter 8, “Advanced Programmable Interrupt Controller (APIC)”). The APIC archi-

tecture was introduced into the IA-32 processors with the Pentium processor.

• A second-level cache (level 2, L2). For the Pentium 4, Intel Xeon, and P6 family

processors, the L2 cache is included in the processor package and is tightly coupled to the

processor. For the Pentium and Intel486 processors, pins are provided to support an

external L2 cache.

• A third-level cache (level 3, L3). For the Intel Xeon processors, the L3 cache is included in

the processor package and is tightly coupled to the processor.

• Hyper-Threading Technology, an extension to the IA-32 architecture that enables a single

processor core to execute two or more threads of execution concurrently (see Section 7.6,

“Hyper-Threading and Multi-Core Technology”).

These mechanisms are particularly useful in symmetric-multiprocessing (SMP) systems.

However, they can also be used in applications where a IA-32 processor and a special-purpose

processor (such as a communications, graphics, or video processor) share the system bus.

The goals of these multiprocessing mechanisms are:

• To maintain system memory coherency — When two or more processors are attempting

simultaneously to access the same address in system memory, some communication

mechanism or memory access protocol must be available to promote data coherency and,

in some instances, to allow one processor to temporarily lock a memory location.

• To maintain cache consistency — When one processor accesses data cached on another

processor, it must not receive incorrect data. If it modifies data, all other processors that

access that data must receive the modified data.

• To allow predictable ordering of writes to memory — In some circumstances, it is

important that memory writes be observed externally in precisely the same order as

programmed.

1 2 ... 264 265 266 267 268 269 270 271 272 273 274 ... 635 636

Comments to this Manuals

No comments

Intel ARCHITECTURE IA-32 User Manual Page 269

Comments to this Manuals

Related products and manuals for Processors Intel ARCHITECTURE IA-32