Intel ARCHITECTURE IA-32 User Manual download pdf (Page 199)

Vol. 3A 5-23

INTERRUPT AND EXCEPTION HANDLING

In 64-bit mode, the IDT index is formed by scaling the interrupt vector by 16. The first eight

bytes (bytes 7:0) of a 64-bit mode interrupt gate are similar but not identical to legacy 32-bit

interrupt gates. The type field (bits 11:8 in bytes 7:4) is described in Table 3-2. The Interrupt

Stack Table (IST) field (bits 4:0 in bytes 7:4) is used by the stack switching mechanisms

described in Section 5.14.5, “Interrupt Stack Table.” Bytes 11:8 hold the upper 32 bits of the

target RIP (interrupt segment offset) in canonical form. A general-protection exception (#GP) is

generated if software attempts to reference an interrupt gate with a target RIP that is not in

canonical form.

The target code segment referenced by the interrupt gate must be a 64-bit code segment

(CS.L = 1, CS.D = 0). If the target is not a 64-bit code segment, a general-protection exception

(#GP) is generated with the IDT vector number reported as the error code.

Only 64-bit interrupt and trap gates can be referenced in IA-32e mode (64-bit mode and compat-

ibility mode). Legacy 32-bit interrupt or trap gate types (0EH or 0FH) are redefined in IA-32e

mode as 64-bit interrupt and trap gate types. No 32-bit interrupt or trap gate type exists in IA-32e

mode. If a reference is made to a 16-bit interrupt or trap gate (06H or 07H), a general-protection

exception (#GP(0)) is generated.

5.14.2 64-Bit Mode Stack Frame

In legacy mode, the size of an IDT entry (16 bits or 32 bits) determines the size of interrupt-

stack-frame pushes. SS:ESP is pushed only on a CPL change. In 64-bit mode, the size of inter-

rupt stack-frame pushes is fixed at eight bytes. This is because only 64-bit mode gates can be

referenced. 64-bit mode also pushes SS:RSP unconditionally, rather than only on a CPL change.

Aside from error codes, pushing SS:RSP unconditionally presents operating systems with a

consistent interrupt-stackframe size across all interrupts. Interrupt service-routine entry points

that handle interrupts generated by the INTn instruction or external INTR# signal can push an

additional error code place-holder to maintain consistency.

In legacy mode, the stack pointer may be at any alignment when an interrupt or exception causes

a stack frame to be pushed. This causes the stack frame and succeeding pushes done by an inter-

rupt handler to be at arbitrary alignments. In IA-32e mode, the RSP is aligned to a 16-byte

boundary before pushing the stack frame. The stack frame itself is aligned on a 16-byte

boundary when the interrupt handler is called. The processor can arbitrarily realign the new RSP

on interrupts because the previous (possibly unaligned) RSP is unconditionally saved on the

newly aligned stack. The previous RSP will be automatically restored by a subsequent IRET.

Aligning the stack permits exception and interrupt frames to be aligned on a 16-byte boundary

before interrupts are re-enabled. This allows the stack to be formatted for optimal storage of

16-byte XMM registers, which enables the interrupt handler to use faster 16-byte aligned loads

and stores (MOVAPS rather than MOVUPS) to save and restore XMM registers.

Although the RSP alignment is always performed when LMA = 1, it is only of consequence for

the kernel-mode case where there is no stack switch or IST used. For a stack switch or IST, the

OS would have presumably put suitably aligned RSP values in the TSS.

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Intel ARCHITECTURE IA-32 User Manual Page 199