Intel ARCHITECTURE IA-32 User Manual download pdf (Page 610)

100

101

17-18 Vol. 3A

IA-32 ARCHITECTURE COMPATIBILITY

17.17.7.15 FXAM INSTRUCTION

With the 32-bit x87 FPUs, if the FPU encounters an empty register when executing the FXAM

instruction, it not generate combinations of C0 through C3 equal to 1101 or 1111. The 16-bit

IA-32 math coprocessors may generate these combinations, among others. This difference has

no impact on existing software; it provides a performance upgrade to provide repeatable results.

17.17.7.16 FSAVE AND FSTENV INSTRUCTIONS

With the 32-bit x87 FPUs, the address of a memory operand pointer stored by FSAVE or

FSTENV is undefined if the previous floating-point instruction did not refer to memory

17.17.8 Transcendental Instructions

The floating-point results of the P6 family and Pentium processors for transcendental instruc-

tions in the core range may differ from the Intel486 processors by about 2 or 3 ulps (see “Tran-

scendental Instruction Accuracy” in Chapter 8, “Programming with the x87 FPU,” of the IA-32

Intel® Architecture Software Developer’s Manual, Volume 1). Condition code flag C1 of the

status word may differ as a result. The exact threshold for underflow and overflow will vary by

a few ulps. The P6 family and Pentium processors’ results will have a worst case error of less

than 1 ulp when rounding to the nearest-even and less than 1.5 ulps when rounding in other

modes. The transcendental instructions are guaranteed to be monotonic, with respect to the input

operands, throughout the domain supported by the instruction.

Transcendental instructions may generate different results in the round-up flag (C1) on the

32-bit x87 FPUs. The round-up flag is undefined for these instructions on the 16-bit IA-32 math

coprocessors. This difference has no impact on existing software.

17.17.9 Obsolete Instructions

The 8087 math coprocessor instructions FENI and FDISI and the Intel 287 math coprocessor

instruction FSETPM are treated as integer NOP instructions in the 32-bit x87 FPUs. If these

opcodes are detected in the instruction stream, no specific operation is performed and no internal

states are affected.

17.17.10WAIT/FWAIT Prefix Differences

On the Intel486 processor, when a WAIT/FWAIT instruction precedes a floating-point instruc-

tion (one which itself automatically synchronizes with the previous floating-point instruction),

the WAIT/FWAIT instruction is treated as a no-op. Pending floating-point exceptions from a

previous floating-point instruction are processed not on the WAIT/FWAIT instruction but on the

floating-point instruction following the WAIT/FWAIT instruction. In such a case, the report of

a floating-point exception may appear one instruction later on the Intel486 processor than on a

P6 family or Pentium FPU, or on Intel 387 math coprocessor.

1 2 ... 605 606 607 608 609 610 611 612 613 614 615 ... 635 636

Comments to this Manuals

No comments

Intel ARCHITECTURE IA-32 User Manual Page 610

Comments to this Manuals

Related products and manuals for Processors Intel ARCHITECTURE IA-32