Intel ARCHITECTURE IA-32 User Manual download pdf (Page 383)

100

101

Vol. 3A 9-9

PROCESSOR MANAGEMENT AND INITIALIZATION

9.4 MODEL-SPECIFIC REGISTERS (MSRS)

The Pentium 4, Intel Xeon, P6 family, and Pentium processors contain a model-specific registers

(MSRs). These registers are by definition implementation specific; that is, they are not guaran-

teed to be supported on future IA-32 processors and/or to have the same functions. The MSRs

are provided to control a variety of hardware- and software-related features, including:

• The performance-monitoring counters (see Section 18.10, “Performance Monitoring

Overview”).

• (Pentium 4, Intel Xeon, and P6 family processors only.) Debug extensions (see Section

18.4, “Last Branch Recording Overview”).

• (Pentium 4, Intel Xeon, and P6 family processors only.) The machine-check exception

capability and its accompanying machine-check architecture (see Chapter 14, “Machine-

Check Architecture”).

• (Pentium 4, Intel Xeon, and P6 family processors only.) The MTRRs (see Section 10.11,

“Memory Type Range Registers (MTRRs)”).

The MSRs can be read and written to using the RDMSR and WRMSR instructions, respectively.

When performing software initialization of a Pentium 4, Intel Xeon, P6 family, or Pentium

processor, many of the MSRs will need to be initialized to set up things like performance-moni-

toring events, run-time machine checks, and memory types for physical memory.

The list of available performance-monitoring counters for the Pentium 4, Intel Xeon, P6 family,

and Pentium processors is given in Appendix A, “Performance-Monitoring Events,” and the list

of available MSRs for the Pentium 4, Intel Xeon, P6 family, and Pentium processors is given in

Appendix B, “Model-Specific Registers (MSRs).” The references earlier in this section show

where the functions of the various groups of MSRs are described in this manual.

9.5 MEMORY TYPE RANGE REGISTERS (MTRRS)

Memory type range registers (MTRRs) were introduced into the IA-32 architecture with the

Pentium Pro processor. They allow the type of caching (or no caching) to be specified in system

memory for selected physical address ranges. They allow memory accesses to be optimized for

various types of memory such as RAM, ROM, frame buffer memory, and memory-mapped I/O

devices.

In general, initializing the MTRRs is normally handled by the software initialization code or

BIOS and is not an operating system or executive function. At the very least, all the MTRRs

must be cleared to 0, which selects the uncached (UC) memory type. See Section 10.11,

“Memory Type Range Registers (MTRRs),” for detailed information on the MTRRs.

1 2 ... 378 379 380 381 382 383 384 385 386 387 388 ... 635 636

Comments to this Manuals

No comments

Intel ARCHITECTURE IA-32 User Manual Page 383

Comments to this Manuals

Related products and manuals for Processors Intel ARCHITECTURE IA-32