Intel ARCHITECTURE IA-32 User Manual download pdf (Page 185)

Vol. 3A 5-9

INTERRUPT AND EXCEPTION HANDLING

5.8.1 Masking Maskable Hardware Interrupts

The IF flag can disable the servicing of maskable hardware interrupts received on the

processor’s INTR pin or through the local APIC (see Section 5.3.2, “Maskable Hardware Inter-

rupts”). When the IF flag is clear, the processor inhibits interrupts delivered to the INTR pin or

through the local APIC from generating an internal interrupt request; when the IF flag is set,

interrupts delivered to the INTR or through the local APIC pin are processed as normal external

interrupts.

The IF flag does not affect non-maskable interrupts (NMIs) delivered to the NMI pin or delivery

mode NMI messages delivered through the local APIC, nor does it affect processor generated

exceptions. As with the other flags in the EFLAGS register, the processor clears the IF flag in

response to a hardware reset.

The fact that the group of maskable hardware interrupts includes the reserved interrupt and

exception vectors 0 through 32 can potentially cause confusion. Architecturally, when the IF

flag is set, an interrupt for any of the vectors from 0 through 32 can be delivered to the processor

through the INTR pin and any of the vectors from 16 through 32 can be delivered through the

local APIC. The processor will then generate an interrupt and call the interrupt or exception

handler pointed to by the vector number. So for example, it is possible to invoke the page-fault

handler through the INTR pin (by means of vector 14); however, this is not a true page-fault

exception. It is an interrupt. As with the INT n instruction (see Section 5.4.2, “Software-Gener-

ated Exceptions”), when an interrupt is generated through the INTR pin to an exception vector,

the processor does not push an error code on the stack, so the exception handler may not operate

correctly.

The IF flag can be set or cleared with the STI (set interrupt-enable flag) and CLI (clear interrupt-

enable flag) instructions, respectively. These instructions may be executed only if the CPL is

equal to or less than the IOPL. A general-protection exception (#GP) is generated if they are

executed when the CPL is greater than the IOPL. (The effect of the IOPL on these instructions

is modified slightly when the virtual mode extension is enabled by setting the VME flag in

control register CR4: see Section 15.3, “Interrupt and Exception Handling in Virtual-8086

Mode.” Behavior is also impacted by the PVI flag: see Section 15.4, “Protected-Mode Virtual

Interrupts.”

The IF flag is also affected by the following operations:

• The PUSHF instruction stores all flags on the stack, where they can be examined and

modified. The POPF instruction can be used to load the modified flags back into the

EFLAGS register.

• Task switches and the POPF and IRET instructions load the EFLAGS register; therefore,

they can be used to modify the setting of the IF flag.

• When an interrupt is handled through an interrupt gate, the IF flag is automatically cleared,

which disables maskable hardware interrupts. (If an interrupt is handled through a trap

gate, the IF flag is not cleared.)

See the descriptions of the CLI, STI, PUSHF, POPF, and IRET instructions in Chapter 3,

“Instruction Set Reference, A-M,” in the IA-32 Intel® Architecture Software Developer’s

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