Intel ARCHITECTURE IA-32 User Manual download pdf (Page 601)

Vol. 3A 17-9

IA-32 ARCHITECTURE COMPATIBILITY

As on the Intel 286 and Intel386 processors, the MP (monitor coprocessor) flag (bit 1 of register

CR0) determines whether the WAIT/FWAIT instructions or waiting-type floating-point instruc-

tions trap when the context of the x87 FPU is different from that of the currently-executing task.

If the MP and TS flag are set, then a WAIT/FWAIT instruction and waiting instructions will

cause a device-not-available exception (interrupt vector 7). The MP flag is used on the Intel 286

and Intel386 processors to support the use of a WAIT/FWAIT instruction to wait on a device

other than a math coprocessor. The device reports its status through the BUSY# pin. Since the

P6 family, Pentium, and Intel486 processors do not have such a pin, the MP flag has no relevant

use and should be set to 1 for normal operation.

17.17.2 x87 FPU Status Word

This section identifies differences to the x87 FPU status word for the different IA-32 processors

and math coprocessors, the reason for the differences, and their impact on software.

17.17.2.1 CONDITION CODE FLAGS (C0 THROUGH C3)

The following information pertains to differences in the use of the condition code flags (C0

through C3) located in bits 8, 9, 10, and 14 of the x87 FPU status word.

After execution of an FINIT instruction or a hardware reset on a 32-bit x87 FPU, the condition

code flags are set to 0. The same operations on a 16-bit IA-32 math coprocessor leave these flags

intact (they contain their prior value). This difference in operation has no impact on software

and provides a consistent state after reset.

Transcendental instruction results in the core range of the P6 family and Pentium processors may

differ from the Intel486 DX processor and Intel 487 SX math coprocessor by 2 to 3 units in the

last place (ulps)—(see “Transcendental Instruction Accuracy” in Chapter 8, “Programming with

the x87 FPU,” of the IA-32 Intel® Architecture Software Developer’s Manual, Volume 1). As a

result, the value saved in the C1 flag may also differ.

After an incomplete FPREM/FPREM1 instruction, the C0, C1, and C3 flags are set to 0 on the

32-bit x87 FPUs. After the same operation on a 16-bit IA-32 math coprocessor, these flags are

left intact.

On the 32-bit x87 FPUs, the C2 flag serves as an incomplete flag for the FTAN instruction. On

the 16-bit IA-32 math coprocessors, the C2 flag is undefined for the FPTAN instruction. This

difference has no impact on software, because Intel 287 or 8087 programs do not check C2 after

an FPTAN instruction. The use of this flag on later processors allows fast checking of operand

range.

17.17.2.2 STACK FAULT FLAG

When unmasked stack overflow or underflow occurs on a 32-bit x87 FPU, the IE flag (bit 0) and

the SF flag (bit 6) of the x87 FPU status word are set to indicate a stack fault and condition code

flag C1 is set or cleared to indicate overflow or underflow, respectively. When unmasked stack

overflow or underflow occurs on a 16-bit IA-32 math coprocessor, only the IE flag is set. Bit 6

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Intel ARCHITECTURE IA-32 User Manual Page 601