Intel ARCHITECTURE IA-32 User Manual download pdf (Page 299)

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Vol. 3A 7-31

MULTIPLE-PROCESSOR MANAGEMENT

7.8.12 Self Modifying Code

IA-32 processors supporting Hyper-Threading Technology support self-modifying code, where

data writes modify instructions cached or currently in flight. They also support cross-modifying

code, where on an MP system writes generated by one processor modify instructions cached or

currently in flight on another. See Section 7.1.3, “Handling Self- and Cross-Modifying Code,”

for a description of the requirements for self- and cross-modifying code in an IA-32 processor.

7.8.13 Implementation-Specific HT Technology Facilities

The following non-architectural facilities are implementation-specific in IA-32 processors

supporting Hyper-Threading Technology:

• Caches

• Translation lookaside buffers (TLBs)

• Thermal monitoring facilities

The Intel Xeon processor MP implementation is described in the following sections.

7.8.13.1 Processor Caches

For the Intel Xeon processor MP, the caches are shared. Any cache manipulation instruction that

is executed on one logical processor has a global effect on the cache hierarchy of the physical

processor. Note the following:

• WBINVD instruction — The entire cache hierarchy is invalidated after modified data is

written back to memory. All logical processors are stopped from executing until after the

write-back and invalidate operation is completed. A special bus cycle is sent to all caching

agents.

• INVD instruction — The entire cache hierarchy is invalidated without writing back

modified data to memory. All logical processors are stopped from executing until after the

invalidate operation is completed. A special bus cycle is sent to all caching agents.

• CLFLUSH instruction — The specified cache line is invalidated from the cache

hierarchy after any modified data is written back to memory and a bus cycle is sent to all

caching agents, regardless of which logical processor caused the cache line to be filled.

• CD flag in control register CR0 — Each logical processor has its own CR0 control

ORed together, such that when any logical processor sets its CD flag, the entire cache is

nominally disabled.

7.8.13.2 Processor Translation Lookaside Buffers (TLBs)

In an Intel Xeon processor MP, data cache TLBs are shared. The instruction cache TLB is dupli-

cated in each logical processor.

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