Intel ARCHITECTURE IA-32 User Manual download pdf (Page 501)

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101

Vol. 3A 12-3

SSE, SSE2 AND SSE3 SYSTEM PROGRAMMING

NOTE

The OSFXSR and OSXMMEXCPT bits in control register CR4 must be set

by the operating system. The processor has no other way of detecting

operating-system support for the FXSAVE and FXRSTOR instructions or for

handling SIMD floating-point exceptions.

3. Clear CR0.EM[bit 2] = 0. This action disables emulation of the x87 FPU, which is required

when executing SSE/SSE2/SSE3 instructions (see Section 2.5, “Control Registers”).

4. Clear CR0.MP[bit 1] = 0. This setting is the required setting for all IA-32 processors that

support the SSE/SSE2/SSE3 extensions (see Section 9.2.1, “Configuring the x87 FPU

Environment”).

Table 12-1 shows the actions of the processor when an SSE/SSE2/SSE3 instruction is executed,

depending on the:

• OSFXSR and OSXMMEXCPT flags in control register CR4

• SSE/SSE2/SSE3 feature flags returned by CPUID

• EM, MP, and TS flags in control register CR0

Table 12-1. Action Taken for Combinations of OSFXSR, OSXMMEXCPT, SSE, SSE2,

SSE3, EM, MP, and TS

CR4 CPUID CR0 Flags

OSFXSR OSXMMEXCPT

SSE,

SSE2,

SSE3 EM MP

TS Action

X X 1 X #UD exception.

1 X 0 X 1 X #UD exception.

1 X 1 1 1 X #UD exception.

1 0 1 0 1 0 Execute instruction; #UD exception if

unmasked SIMD floating-point exception is

detected.

1 1 1 0 1 0 Execute instruction; #XF exception if

unmasked SIMD floating-point exception is

detected.

1 X 1 0 1 1 #NM exception.

NOTES:

1. For execution of any SSE/SSE2/SSE3 instruction except the PAUSE, PREFETCHh, SFENCE,

LFENCE, MFENCE, MOVNTI, and CLFLUSH instructions.

2. For processors that support the MMX instructions, the MP flag should be set.

3. X — Don’t care.

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