Intel ARCHITECTURE IA-32 User Manual download pdf (Page 197)

100

101

Vol. 3A 5-21

INTERRUPT AND EXCEPTION HANDLING

5.13 ERROR CODE

When an exception condition is related to a specific segment, the processor pushes an error code

onto the stack of the exception handler (whether it is a procedure or task). The error code has

the format shown in Figure 5-6. The error code resembles a segment selector; however, instead

of a TI flag and RPL field, the error code contains 3 flags:

EXT External event (bit 0) — When set, indicates that an event external to the

program, such as a hardware interrupt, caused the exception.

IDT Descriptor location (bit 1) — When set, indicates that the index portion of the

error code refers to a gate descriptor in the IDT; when clear, indicates that the

index refers to a descriptor in the GDT or the current LDT.

TI GDT/LDT (bit 2) — Only used when the IDT flag is clear. When set, the TI

flag indicates that the index portion of the error code refers to a segment or gate

descriptor in the LDT; when clear, it indicates that the index refers to a

descriptor in the current GDT.

The segment selector index field provides an index into the IDT, GDT, or current LDT to the

segment or gate selector being referenced by the error code. In some cases the error code is null

(that is, all bits in the lower word are clear). A null error code indicates that the error was not

caused by a reference to a specific segment or that a null segment descriptor was referenced in

an operation.

The format of the error code is different for page-fault exceptions (#PF). See the “Interrupt

14—Page-Fault Exception (#PF)” section in this chapter.

The error code is pushed on the stack as a doubleword or word (depending on the default inter-

rupt, trap, or task gate size). To keep the stack aligned for doubleword pushes, the upper half of

the error code is reserved. Note that the error code is not popped when the IRET instruction is

executed to return from an exception handler, so the handler must remove the error code before

executing a return.

Error codes are not pushed on the stack for exceptions that are generated externally (with the

INTR or LINT[1:0] pins) or the INT n instruction, even if an error code is normally produced

for those exceptions.

Figure 5-6. Error Code

Reserved

123

Segment Selector Index

1 2 ... 192 193 194 195 196 197 198 199 200 201 202 ... 635 636

Comments to this Manuals

No comments

Intel ARCHITECTURE IA-32 User Manual Page 197

Comments to this Manuals

Related products and manuals for Processors Intel ARCHITECTURE IA-32