Intel ARCHITECTURE IA-32 User Manual download pdf (Page 220)

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INTERRUPT AND EXCEPTION HANDLING

Saved Instruction Pointer

The saved contents of CS and EIP registers normally point to the instruction that generated the

exception. If the exception occurred while loading segment descriptors for the segment selectors

in a new TSS, the CS and EIP registers point to the first instruction in the new task. If the excep-

tion occurred while accessing a gate descriptor, the CS and EIP registers point to the instruction

that invoked the access (for example a CALL instruction that references a call gate).

Program State Change

If the segment-not-present exception occurs as the result of loading a register (CS, DS, SS, ES,

FS, GS, or LDTR), a program-state change does accompany the exception because the register

is not loaded. Recovery from this exception is possible by simply loading the missing segment

into memory and setting the present flag in the segment descriptor.

If the segment-not-present exception occurs while accessing a gate descriptor, a program-state

change does not accompany the exception. Recovery from this exception is possible merely by

setting the present flag in the gate descriptor.

If a segment-not-present exception occurs during a task switch, it can occur before or after the

commit-to-new-task point (see Section 6.3, “Task Switching”). If it occurs before the commit

point, no program state change occurs. If it occurs after the commit point, the processor will load

all the state information from the new TSS (without performing any additional limit, present, or

type checks) before it generates the exception. The segment-not-present exception handler

should not rely on being able to use the segment selectors found in the CS, SS, DS, ES, FS, and

GS registers without causing another exception. (See the Program State Change description for

“Interrupt 10—Invalid TSS Exception (#TS)” in this chapter for additional information on how

to handle this situation.)

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