Intel ARCHITECTURE IA-32 User Manual download pdf (Page 527)

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Vol. 3A 14-1

CHAPTER 14

MACHINE-CHECK ARCHITECTURE

This chapter describes the machine-check architecture and machine-check exception mecha-

nism found in the Pentium 4, Intel Xeon, and P6 family processors. See Chapter 5, “Interrupt

18—Machine-Check Exception (#MC),” for more information on machine-check exceptions. A

brief description of the Pentium processor’s machine check capability is also given.

14.1 MACHINE-CHECK EXCEPTIONS AND ARCHITECTURE

The Pentium 4, Intel Xeon, and P6 family processors implement a machine-check architecture

that provides a mechanism for detecting and reporting hardware (machine) errors, such as:

system bus errors, ECC errors, parity errors, cache errors, and TLB errors. It consists of a set of

model-specific registers (MSRs) that are used to set up machine checking and additional banks

of MSRs used for recording errors that are detected.

The processor signals the detection of a machine-check error by generating a machine-check

exception (#MC), which is an abort class exception. The implementation of the machine-check

architecture does not ordinarily permit the processor to be restarted reliably after generating a

machine-check exception. However, the machine-check-exception handler can collect informa-

tion about the machine-check error from the machine-check MSRs.

14.2 COMPATIBILITY WITH PENTIUM

PROCESSOR

The Pentium 4, Intel Xeon, and P6 family processors support and extend the machine-check

exception mechanism introduced in the Pentium processor. The Pentium processor reports the

following machine-check errors:

• data parity errors during read cycles

• unsuccessful completion of a bus cycle

The above errors are reported using the P5_MC_TYPE and P5_MC_ADDR MSRs (implemen-

tation specific for the Pentium processor). Use the RDMSR instruction to read these MSRs. See

Appendix B, “Model-Specific Registers (MSRs),” for the addresses.

The machine-check error reporting mechanism that Pentium processors use is similar to that

used in Pentium 4, Intel Xeon, and P6 family processors. When an error is detected, it is

recorded in P5_MC_TYPE and P5_MC_ADDR; the processor then generates a machine-check

exception (#MC).

See Section 14.3.3, “Mapping of the Pentium

Processor Machine-Check Errors to the Machine-

Check Architecture,” and Section 14.7.3, “Pentium

Processor Machine-Check Exception

Handling,” for information on compatibility between machine-check code written to run on the

Pentium processors and code written to run on P6 family processors.

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