Intel ARCHITECTURE IA-32 User Manual download pdf (Page 607)

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Vol. 3A 17-15

IA-32 ARCHITECTURE COMPATIBILITY

17.17.6.14 FLOATING-POINT ERROR EXCEPTION (#MF)

In real mode and protected mode (not including virtual-8086 mode), interrupt vector 16 must

point to the floating-point exception handler. In virtual 8086 mode, the virtual-8086 monitor can

be programmed to accommodate a different location of the interrupt vector for floating-point

exceptions.

17.17.7 Changes to Floating-Point Instructions

This section identifies the differences in floating-point instructions for the various Intel FPU and

math coprocessor architectures, the reason for the differences, and their impact on software.

17.17.7.1 FDIV, FPREM, AND FSQRT INSTRUCTIONS

The 32-bit x87 FPUs support operations on denormalized operands and, when detected, an

underflow exception can occur, for compatibility with the IEEE Standard 754. The 16-bit IA-32

math coprocessors do not operate on denormalized operands or return underflow results.

Instead, they generate an invalid-operation exception when they detect an underflow condition.

An existing underflow exception handler will require change only if it gives different treatment

to different opcodes. Also, it is possible that fewer invalid-operation exceptions will occur.

17.17.7.2 FSCALE INSTRUCTION

With the 32-bit x87 FPUs, the range of the scaling operand is not restricted. If (0 < | ST(1) < 1),

the scaling factor is 0; therefore, ST(0) remains unchanged. If the rounded result is not exact or

if there was a loss of accuracy (masked underflow), the precision exception is signaled. With the

16-bit IA-32 math coprocessors, the range of the scaling operand is restricted. If

(0 < | ST(1) | < 1), the result is undefined and no exception is signaled. The impact of this differ-

ence on exiting software is that different results are delivered on the 32-bit and 16-bit FPUs and

math coprocessors when (0 < | ST(1) | < 1).

17.17.7.3 FPREM1 INSTRUCTION

The 32-bit x87 FPUs compute a partial remainder according to IEEE Standard 754. This instruc-

tion does not exist on the 16-bit IA-32 math coprocessors. The availability of the FPREM1

instruction has is no impact on existing software.

17.17.7.4 FPREM INSTRUCTION

On the 32-bit x87 FPUs, the condition code flags C0, C3, C1 in the status word correctly reflect

the three low-order bits of the quotient following execution of the FPREM instruction. On the

16-bit IA-32 math coprocessors, the quotient bits are incorrect when performing a reduction of

(64

+ M) when (N ≥ 1) and M is 1 or 2. This difference does not affect existing software; soft-

ware that works around the bug should not be affected.

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