Intel ARCHITECTURE IA-32 User Manual download pdf (Page 325)

100

101

Vol. 3A 8-1

CHAPTER 8

ADVANCED PROGRAMMABLE

INTERRUPT CONTROLLER (APIC)

The Advanced Programmable Interrupt Controller (APIC), referred to in the following sections

as the local APIC, was introduced into the IA-32 processors with the Pentium processor (see

Section 17.26., “Advanced Programmable Interrupt Controller (APIC)”) and is included in the

P6 family, Pentium 4 and Intel Xeon processors (see Section 8.4.2, “Presence of the Local

APIC”). The local APIC performs two primary functions for the processor:

• It receives interrupts from the processor’s interrupt pins, from internal sources and from an

external I/O APIC (or other external interrupt controller). It sends these to the processor

core for handling.

• In multiple processor (MP) systems, it sends and receives interprocessor interrupt (IPI)

messages to and from other IA-32 processors on the system bus. IPI messages can be used

to distribute interrupts among the processors in the system or to execute system wide

functions (such as, booting up processors or distributing work among a group of

processors).

The external I/O APIC is part of Intel’s system chip set. Its primary function is to receive

external interrupt events from the system and its associated I/O devices and relay them to the

local APIC as interrupt messages. In MP systems, the I/O APIC also provides a mechanism for

distributing external interrupts to the local APICs of selected processors or groups of processors

on the system bus.

This chapter provides a description of the local APIC and its programming interface. It also

provides an overview of the interface between the local APIC and the I/O APIC. Contact Intel

for detailed information about the I/O APIC.

When a local APIC has sent an interrupt to its processor core for handling, the processor uses

the interrupt and exception handling mechanism described in Chapter 5, “Interrupt and Excep-

tion Handling.” See Section 5.1, “Interrupt and Exception Overview,” for an introduction to

interrupt and exception handling in the IA-32 architecture.

8.1 LOCAL AND I/O APIC OVERVIEW

Each local APIC consists of a set of APIC registers (see Table 8-1) and associated hardware that

control the delivery of interrupts to the processor core and the generation of IPI messages. The

APIC registers are memory mapped and can be read and written to using the MOV instruction.

1 2 ... 320 321 322 323 324 325 326 327 328 329 330 ... 635 636

Comments to this Manuals

No comments

Intel ARCHITECTURE IA-32 User Manual Page 325

Comments to this Manuals

Related products and manuals for Processors Intel ARCHITECTURE IA-32