Intel ARCHITECTURE IA-32 User Manual download pdf (Page 275)

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Vol. 3A 7-7

MULTIPLE-PROCESSOR MANAGEMENT

To write cross-modifying code and insure that it is compliant with current and future versions

of the IA-32 architecture, the following processor synchronization algorithm must be imple-

mented:

(* Action of Modifying Processor *)

Memory_Flag ← 0; (* Set Memory_Flag to value other than 1 *)

Store modified code (as data) into code segment;

Memory_Flag ← 1;

(* Action of Executing Processor *)

WHILE (Memory_Flag ≠ 1)

Wait for code to update;

ELIHW;

Execute serializing instruction; (* For example, CPUID instruction *)

Begin executing modified code;

(The use of this option is not required for programs intended to run on the Intel486 processor,

but is recommended to insure compatibility with the Pentium 4, Intel Xeon, P6 family, and

Pentium processors.)

Like self-modifying code, cross-modifying code will execute at a lower level of performance

than non-cross-modifying (normal) code, depending upon the frequency of modification and

specific characteristics of the code.

7.1.4 Effects of a LOCK Operation on Internal Processor

Caches

For the Intel486 and Pentium processors, the LOCK# signal is always asserted on the bus during

a LOCK operation, even if the area of memory being locked is cached in the processor.

For the Pentium 4, Intel Xeon, and P6 family processors, if the area of memory being locked

during a LOCK operation is cached in the processor that is performing the LOCK operation as

write-back memory and is completely contained in a cache line, the processor may not assert the

LOCK# signal on the bus. Instead, it will modify the memory location internally and allow it’s

cache coherency mechanism to insure that the operation is carried out atomically. This operation

is called “cache locking.” The cache coherency mechanism automatically prevents two or more

processors that have cached the same area of memory from simultaneously modifying data in

that area.

7.2 MEMORY ORDERING

The term memory ordering refers to the order in which the processor issues reads (loads) and

writes (stores) through the system bus to system memory. The IA-32 architecture supports

several memory ordering models depending on the implementation of the architecture. For

example, the Intel386 processor enforces program ordering (generally referred to as strong

ordering), where reads and writes are issued on the system bus in the order they occur in the

instruction stream under all circumstances.

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