Intel ARCHITECTURE IA-32 User Manual download pdf (Page 484)

10-44 Vol. 3A

MEMORY CACHE CONTROL

The values in all the entries of the PAT can be changed by writing to the IA32_CR_PAT MSR

using the WRMSR instruction. The IA32_CR_PAT MSR is read and write accessible (use of

the RDMSR and WRMSR instructions, respectively) to software operating at a CPL of 0.

Table 10-10 shows the allowable encoding of the entries in the PAT. Attempting to write an

undefined memory type encoding into the PAT causes a general-protection (#GP) exception

to be generated.

NOTE

In a multiple processor system, the PATs of all processors must contain the

same values.

The operating system is responsible for insuring that changes to a PAT entry occur in a manner

that maintains the consistency of the processor caches and translation lookaside buffers (TLB).

This is accomplished by following the procedure as specified in Section 10.11.8, “MTRR

Considerations in MP Systems,” for changing the value of an MTRR in a multiple processor

system. It requires a specific sequence of operations that includes flushing the processors caches

and TLBs.

The PAT allows any memory type to be specified in the page tables, and therefore it is possible

to have a single physical page mapped to two or more different linear addresses, each with

different memory types. Intel does not support this practice because it may lead to undefined

operations that can result in a system failure. In particular, a WC page must never be aliased to

a cacheable page because WC writes may not check the processor caches. When remapping a

page that was previously mapped as a cacheable memory type to a WC page, an operating

system can avoid this type of aliasing by doing the following:

1. Remove the previous mapping to a cacheable memory type in the page tables; that is, make

them not present.

2. Flush the TLBs of processors that may have used the mapping, even speculatively.

3. Create a new mapping to the same physical address with a new memory type, for instance,

WC.

4. Flush the caches on all processors that may have used the mapping previously. Note on

processors that support self-snooping, CPUID feature flag bit 27, this step is unnecessary.

Operating systems that use a page directory as a page table (to map large pages) and enable page

size extensions must carefully scrutinize the use of the PAT index bit for the 4-KByte page-table

entries. The PAT index bit for a page-table entry (bit 7) corresponds to the page size bit in a page-

directory entry. Therefore, the operating system can only use PAT entries PA0 through PA3

when setting the caching type for a page table that is also used as a page directory. If the oper-

ating system attempts to use PAT entries PA4 through PA7 when using this memory as a page

table, it effectively sets the PS bit for the access to this memory as a page directory.

For compatibility with earlier IA-32 processors that do not support the PAT, care should be taken

in selecting the encodings for entries in the PAT (see Section 10.12.5, “PAT Compatibility with

Earlier IA-32 Processors”).

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Intel ARCHITECTURE IA-32 User Manual Page 484