Intel ARCHITECTURE IA-32 User Manual download pdf (Page 457)

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Vol. 3A 10-17

MEMORY CACHE CONTROL

4. Setting the PCD and PWT flags to opposite values is considered model-specific for the WP

and WC memory types and architecturally-defined for the WB, WT, and UC memory

types.

10.5.2.2 Selecting Memory Types for Pentium 4, Intel Xeon,

and Pentium III Processors

The Pentium 4, Intel Xeon, and Pentium III processors use the PAT to select effective page-level

memory types. Here, a memory type for a page is selected by the MTRRs and the value in a PAT

entry that is selected with the PAT, PCD and PWT bits in a page-table or page-directory entry

(see Section 10.12.3, “Selecting a Memory Type from the PAT”). Table 10-7 describes the

mapping of MTRR memory types and PAT entry types to effective memory types, when normal

caching is in effect (the CD and NW flags in control register CR0 are clear). The combinations

shown in gray are implementation-defined for the Pentium 4, Intel Xeon, and Pentium III proces-

sors. System designers are encouraged to avoid the implementation-defined combinations.

Table 10-7. Effective Page-Level Memory Types for Pentium III, Pentium 4,

and Intel Xeon Processors

MTRR Memory Type PAT Entry Value Effective Memory Type

UC UC UC

UC- UC

WC WC

WT UC

WB UC

WP UC

WC UC UC

UC- WC

WC WC

WT UC

2,3

WB WC

WP UC

2,3

WT UC UC

UC- UC

WC WC

WT WT

WB WT

WP WP

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